/*
 * Copyright (c) 2017 Trail of Bits, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#pragma once

#include <cstdint>

namespace remill {

class Instruction;

namespace aarch64 {

enum class InstName : uint16_t {
  INVALID,
  ABS,
  ADC,
  ADCS,
  ADD,
  ADDHN,
  ADDP,
  ADDS,
  ADDV,
  ADR,
  ADRP,
  AESD,
  AESE,
  AESIMC,
  AESMC,
  AND,
  ANDS,
  ASRV,
  B,
  BFM,
  BIC,
  BICS,
  BIF,
  BIT,
  BL,
  BLR,
  BR,
  BRK,
  BSL,
  CAS,
  CASA,
  CASAB,
  CASAH,
  CASAL,
  CASALB,
  CASALH,
  CASB,
  CASH,
  CASL,
  CASLB,
  CASLH,
  CASP,
  CASPA,
  CASPAL,
  CASPL,
  CBNZ,
  CBZ,
  CCMN,
  CCMP,
  CLREX,
  CLS,
  CLZ,
  CMEQ,
  CMGE,
  CMGT,
  CMHI,
  CMHS,
  CMLE,
  CMLT,
  CMTST,
  CNT,
  CRC32B,
  CRC32CB,
  CRC32CH,
  CRC32CW,
  CRC32CX,
  CRC32H,
  CRC32W,
  CRC32X,
  CSEL,
  CSINC,
  CSINV,
  CSNEG,
  DCPS1,
  DCPS2,
  DCPS3,
  DMB,
  DRPS,
  DSB,
  DUP,
  EON,
  EOR,
  ERET,
  ESB,
  EXT,
  EXTR,
  FABD,
  FABS,
  FACGE,
  FACGT,
  FADD,
  FADDP,
  FCCMP,
  FCCMPE,
  FCMEQ,
  FCMGE,
  FCMGT,
  FCMLE,
  FCMLT,
  FCMP,
  FCMPE,
  FCSEL,
  FCVT,
  FCVTAS,
  FCVTAU,
  FCVTL,
  FCVTMS,
  FCVTMU,
  FCVTN,
  FCVTNS,
  FCVTNU,
  FCVTPS,
  FCVTPU,
  FCVTXN,
  FCVTZS,
  FCVTZU,
  FDIV,
  FMADD,
  FMAX,
  FMAXNM,
  FMAXNMP,
  FMAXNMV,
  FMAXP,
  FMAXV,
  FMIN,
  FMINNM,
  FMINNMP,
  FMINNMV,
  FMINP,
  FMINV,
  FMLA,
  FMLS,
  FMOV,
  FMSUB,
  FMUL,
  FMULX,
  FNEG,
  FNMADD,
  FNMSUB,
  FNMUL,
  FRECPE,
  FRECPS,
  FRECPX,
  FRINTA,
  FRINTI,
  FRINTM,
  FRINTN,
  FRINTP,
  FRINTX,
  FRINTZ,
  FRSQRTE,
  FRSQRTS,
  FSQRT,
  FSUB,
  HINT,
  HLT,
  HVC,
  INS,
  ISB,
  LD1,
  LD1R,
  LD2,
  LD2R,
  LD3,
  LD3R,
  LD4,
  LD4R,
  LDADD,
  LDADDA,
  LDADDAB,
  LDADDAH,
  LDADDAL,
  LDADDALB,
  LDADDALH,
  LDADDB,
  LDADDH,
  LDADDL,
  LDADDLB,
  LDADDLH,
  LDAR,
  LDARB,
  LDARH,
  LDAXP,
  LDAXR,
  LDAXRB,
  LDAXRH,
  LDCLR,
  LDCLRA,
  LDCLRAB,
  LDCLRAH,
  LDCLRAL,
  LDCLRALB,
  LDCLRALH,
  LDCLRB,
  LDCLRH,
  LDCLRL,
  LDCLRLB,
  LDCLRLH,
  LDEOR,
  LDEORA,
  LDEORAB,
  LDEORAH,
  LDEORAL,
  LDEORALB,
  LDEORALH,
  LDEORB,
  LDEORH,
  LDEORL,
  LDEORLB,
  LDEORLH,
  LDLAR,
  LDLARB,
  LDLARH,
  LDNP,
  LDP,
  LDPSW,
  LDR,
  LDRB,
  LDRH,
  LDRSB,
  LDRSH,
  LDRSW,
  LDSET,
  LDSETA,
  LDSETAB,
  LDSETAH,
  LDSETAL,
  LDSETALB,
  LDSETALH,
  LDSETB,
  LDSETH,
  LDSETL,
  LDSETLB,
  LDSETLH,
  LDSMAX,
  LDSMAXA,
  LDSMAXAB,
  LDSMAXAH,
  LDSMAXAL,
  LDSMAXALB,
  LDSMAXALH,
  LDSMAXB,
  LDSMAXH,
  LDSMAXL,
  LDSMAXLB,
  LDSMAXLH,
  LDSMIN,
  LDSMINA,
  LDSMINAB,
  LDSMINAH,
  LDSMINAL,
  LDSMINALB,
  LDSMINALH,
  LDSMINB,
  LDSMINH,
  LDSMINL,
  LDSMINLB,
  LDSMINLH,
  LDTR,
  LDTRB,
  LDTRH,
  LDTRSB,
  LDTRSH,
  LDTRSW,
  LDUMAX,
  LDUMAXA,
  LDUMAXAB,
  LDUMAXAH,
  LDUMAXAL,
  LDUMAXALB,
  LDUMAXALH,
  LDUMAXB,
  LDUMAXH,
  LDUMAXL,
  LDUMAXLB,
  LDUMAXLH,
  LDUMIN,
  LDUMINA,
  LDUMINAB,
  LDUMINAH,
  LDUMINAL,
  LDUMINALB,
  LDUMINALH,
  LDUMINB,
  LDUMINH,
  LDUMINL,
  LDUMINLB,
  LDUMINLH,
  LDUR,
  LDURB,
  LDURH,
  LDURSB,
  LDURSH,
  LDURSW,
  LDXP,
  LDXR,
  LDXRB,
  LDXRH,
  LSLV,
  LSRV,
  MADD,
  MLA,
  MLS,
  MOVI,
  MOVK,
  MOVN,
  MOVZ,
  MRS,
  MSR,
  MSUB,
  MUL,
  MVNI,
  NEG,
  NOP,
  NOT,
  ORN,
  ORR,
  PMUL,
  PMULL,
  PRFM,
  PRFUM,
  PSB,
  RADDHN,
  RBIT,
  RET,
  REV,
  REV16,
  REV32,
  REV64,
  RORV,
  RSHRN,
  RSUBHN,
  SABA,
  SABAL,
  SABD,
  SABDL,
  SADALP,
  SADDL,
  SADDLP,
  SADDLV,
  SADDW,
  SBC,
  SBCS,
  SBFM,
  SCVTF,
  SDIV,
  SEV,
  SEVL,
  SHA1C,
  SHA1H,
  SHA1M,
  SHA1P,
  SHA1SU0,
  SHA1SU1,
  SHA256H,
  SHA256H2,
  SHA256SU0,
  SHA256SU1,
  SHADD,
  SHL,
  SHLL,
  SHRN,
  SHSUB,
  SLI,
  SMADDL,
  SMAX,
  SMAXP,
  SMAXV,
  SMC,
  SMIN,
  SMINP,
  SMINV,
  SMLAL,
  SMLSL,
  SMOV,
  SMSUBL,
  SMULH,
  SMULL,
  SQABS,
  SQADD,
  SQDMLAL,
  SQDMLSL,
  SQDMULH,
  SQDMULL,
  SQNEG,
  SQRDMLAH,
  SQRDMLSH,
  SQRDMULH,
  SQRSHL,
  SQRSHRN,
  SQRSHRUN,
  SQSHL,
  SQSHLU,
  SQSHRN,
  SQSHRUN,
  SQSUB,
  SQXTN,
  SQXTUN,
  SRHADD,
  SRI,
  SRSHL,
  SRSHR,
  SRSRA,
  SSHL,
  SSHLL,
  SSHR,
  SSRA,
  SSUBL,
  SSUBW,
  ST1,
  ST2,
  ST3,
  ST4,
  STADD,
  STADDB,
  STADDH,
  STADDL,
  STADDLB,
  STADDLH,
  STCLR,
  STCLRB,
  STCLRH,
  STCLRL,
  STCLRLB,
  STCLRLH,
  STEOR,
  STEORB,
  STEORH,
  STEORL,
  STEORLB,
  STEORLH,
  STLLR,
  STLLRB,
  STLLRH,
  STLR,
  STLRB,
  STLRH,
  STLXP,
  STLXR,
  STLXRB,
  STLXRH,
  STNP,
  STP,
  STR,
  STRB,
  STRH,
  STSET,
  STSETB,
  STSETH,
  STSETL,
  STSETLB,
  STSETLH,
  STSMAX,
  STSMAXB,
  STSMAXH,
  STSMAXL,
  STSMAXLB,
  STSMAXLH,
  STSMIN,
  STSMINB,
  STSMINH,
  STSMINL,
  STSMINLB,
  STSMINLH,
  STTR,
  STTRB,
  STTRH,
  STUMAX,
  STUMAXB,
  STUMAXH,
  STUMAXL,
  STUMAXLB,
  STUMAXLH,
  STUMIN,
  STUMINB,
  STUMINH,
  STUMINL,
  STUMINLB,
  STUMINLH,
  STUR,
  STURB,
  STURH,
  STXP,
  STXR,
  STXRB,
  STXRH,
  SUB,
  SUBHN,
  SUBS,
  SUQADD,
  SVC,
  SWP,
  SWPA,
  SWPAB,
  SWPAH,
  SWPAL,
  SWPALB,
  SWPALH,
  SWPB,
  SWPH,
  SWPL,
  SWPLB,
  SWPLH,
  SYS,
  SYSL,
  TBL,
  TBNZ,
  TBX,
  TBZ,
  TRN1,
  TRN2,
  UABA,
  UABAL,
  UABD,
  UABDL,
  UADALP,
  UADDL,
  UADDLP,
  UADDLV,
  UADDW,
  UBFM,
  UCVTF,
  UDIV,
  UHADD,
  UHSUB,
  UMADDL,
  UMAX,
  UMAXP,
  UMAXV,
  UMIN,
  UMINP,
  UMINV,
  UMLAL,
  UMLSL,
  UMOV,
  UMSUBL,
  UMULH,
  UMULL,
  UQADD,
  UQRSHL,
  UQRSHRN,
  UQSHL,
  UQSHRN,
  UQSUB,
  UQXTN,
  URECPE,
  URHADD,
  URSHL,
  URSHR,
  URSQRTE,
  URSRA,
  USHL,
  USHLL,
  USHR,
  USQADD,
  USRA,
  USUBL,
  USUBW,
  UZP1,
  UZP2,
  WFE,
  WFI,
  XTN,
  YIELD,
  ZIP1,
  ZIP2,
};

enum class InstForm : uint16_t {
  INVALID,
  ABS_ASIMDMISC_R,
  ABS_ASISDMISC_R,
  ADCS_32_ADDSUB_CARRY,
  ADCS_64_ADDSUB_CARRY,
  ADC_32_ADDSUB_CARRY,
  ADC_64_ADDSUB_CARRY,
  ADDHN_ASIMDDIFF_N,
  ADDP_ASIMDSAME_ONLY,
  ADDP_ASISDPAIR_ONLY,
  ADDS_32S_ADDSUB_EXT,
  ADDS_32S_ADDSUB_IMM,
  ADDS_32_ADDSUB_SHIFT,
  ADDS_64S_ADDSUB_EXT,
  ADDS_64S_ADDSUB_IMM,
  ADDS_64_ADDSUB_SHIFT,
  ADDV_ASIMDALL_ONLY,
  ADD_32_ADDSUB_EXT,
  ADD_32_ADDSUB_IMM,
  ADD_32_ADDSUB_SHIFT,
  ADD_64_ADDSUB_EXT,
  ADD_64_ADDSUB_IMM,
  ADD_64_ADDSUB_SHIFT,
  ADD_ASIMDSAME_ONLY,
  ADD_ASISDSAME_ONLY,
  ADRP_ONLY_PCRELADDR,
  ADR_ONLY_PCRELADDR,
  AESD_B_CRYPTOAES,
  AESE_B_CRYPTOAES,
  AESIMC_B_CRYPTOAES,
  AESMC_B_CRYPTOAES,
  ANDS_32S_LOG_IMM,
  ANDS_32_LOG_SHIFT,
  ANDS_64S_LOG_IMM,
  ANDS_64_LOG_SHIFT,
  AND_32_LOG_IMM,
  AND_32_LOG_SHIFT,
  AND_64_LOG_IMM,
  AND_64_LOG_SHIFT,
  AND_ASIMDSAME_ONLY,
  ASRV_32_DP_2SRC,
  ASRV_64_DP_2SRC,
  ASR_ASRV_32_DP_2SRC,
  ASR_ASRV_64_DP_2SRC,
  ASR_SBFM_32M_BITFIELD,
  ASR_SBFM_64M_BITFIELD,
  AT_SYS_CR_SYSTEM,
  BFC_BFM_32M_BITFIELD,
  BFC_BFM_64M_BITFIELD,
  BFI_BFM_32M_BITFIELD,
  BFI_BFM_64M_BITFIELD,
  BFM_32M_BITFIELD,
  BFM_64M_BITFIELD,
  BFXIL_BFM_32M_BITFIELD,
  BFXIL_BFM_64M_BITFIELD,
  BICS_32_LOG_SHIFT,
  BICS_64_LOG_SHIFT,
  BIC_32_LOG_SHIFT,
  BIC_64_LOG_SHIFT,
  BIC_ASIMDIMM_L_HL,
  BIC_ASIMDIMM_L_SL,
  BIC_ASIMDSAME_ONLY,
  BIF_ASIMDSAME_ONLY,
  BIT_ASIMDSAME_ONLY,
  BLR_64_BRANCH_REG,
  BL_ONLY_BRANCH_IMM,
  BRK_EX_EXCEPTION,
  BR_64_BRANCH_REG,
  BSL_ASIMDSAME_ONLY,
  B_ONLY_BRANCH_IMM,
  B_ONLY_CONDBRANCH,
  CASAB_C32_LDSTEXCL,
  CASAH_C32_LDSTEXCL,
  CASALB_C32_LDSTEXCL,
  CASALH_C32_LDSTEXCL,
  CASAL_C32_LDSTEXCL,
  CASAL_C64_LDSTEXCL,
  CASA_C32_LDSTEXCL,
  CASA_C64_LDSTEXCL,
  CASB_C32_LDSTEXCL,
  CASH_C32_LDSTEXCL,
  CASLB_C32_LDSTEXCL,
  CASLH_C32_LDSTEXCL,
  CASL_C32_LDSTEXCL,
  CASL_C64_LDSTEXCL,
  CASPAL_CP32_LDSTEXCL,
  CASPAL_CP64_LDSTEXCL,
  CASPA_CP32_LDSTEXCL,
  CASPA_CP64_LDSTEXCL,
  CASPL_CP32_LDSTEXCL,
  CASPL_CP64_LDSTEXCL,
  CASP_CP32_LDSTEXCL,
  CASP_CP64_LDSTEXCL,
  CAS_C32_LDSTEXCL,
  CAS_C64_LDSTEXCL,
  CBNZ_32_COMPBRANCH,
  CBNZ_64_COMPBRANCH,
  CBZ_32_COMPBRANCH,
  CBZ_64_COMPBRANCH,
  CCMN_32_CONDCMP_IMM,
  CCMN_32_CONDCMP_REG,
  CCMN_64_CONDCMP_IMM,
  CCMN_64_CONDCMP_REG,
  CCMP_32_CONDCMP_IMM,
  CCMP_32_CONDCMP_REG,
  CCMP_64_CONDCMP_IMM,
  CCMP_64_CONDCMP_REG,
  CINC_CSINC_32_CONDSEL,
  CINC_CSINC_64_CONDSEL,
  CINV_CSINV_32_CONDSEL,
  CINV_CSINV_64_CONDSEL,
  CLREX_BN_SYSTEM,
  CLS_32_DP_1SRC,
  CLS_64_DP_1SRC,
  CLS_ASIMDMISC_R,
  CLZ_32_DP_1SRC,
  CLZ_64_DP_1SRC,
  CLZ_ASIMDMISC_R,
  CMEQ_ASIMDMISC_Z,
  CMEQ_ASIMDSAME_ONLY,
  CMEQ_ASISDMISC_Z,
  CMEQ_ASISDSAME_ONLY,
  CMGE_ASIMDMISC_Z,
  CMGE_ASIMDSAME_ONLY,
  CMGE_ASISDMISC_Z,
  CMGE_ASISDSAME_ONLY,
  CMGT_ASIMDMISC_Z,
  CMGT_ASIMDSAME_ONLY,
  CMGT_ASISDMISC_Z,
  CMGT_ASISDSAME_ONLY,
  CMHI_ASIMDSAME_ONLY,
  CMHI_ASISDSAME_ONLY,
  CMHS_ASIMDSAME_ONLY,
  CMHS_ASISDSAME_ONLY,
  CMLE_ASIMDMISC_Z,
  CMLE_ASISDMISC_Z,
  CMLT_ASIMDMISC_Z,
  CMLT_ASISDMISC_Z,
  CMN_ADDS_32S_ADDSUB_EXT,
  CMN_ADDS_32S_ADDSUB_IMM,
  CMN_ADDS_32_ADDSUB_SHIFT,
  CMN_ADDS_64S_ADDSUB_EXT,
  CMN_ADDS_64S_ADDSUB_IMM,
  CMN_ADDS_64_ADDSUB_SHIFT,
  CMP_SUBS_32S_ADDSUB_EXT,
  CMP_SUBS_32S_ADDSUB_IMM,
  CMP_SUBS_32_ADDSUB_SHIFT,
  CMP_SUBS_64S_ADDSUB_EXT,
  CMP_SUBS_64S_ADDSUB_IMM,
  CMP_SUBS_64_ADDSUB_SHIFT,
  CMTST_ASIMDSAME_ONLY,
  CMTST_ASISDSAME_ONLY,
  CNEG_CSNEG_32_CONDSEL,
  CNEG_CSNEG_64_CONDSEL,
  CNT_ASIMDMISC_R,
  CRC32B_32C_DP_2SRC,
  CRC32CB_32C_DP_2SRC,
  CRC32CH_32C_DP_2SRC,
  CRC32CW_32C_DP_2SRC,
  CRC32CX_64C_DP_2SRC,
  CRC32H_32C_DP_2SRC,
  CRC32W_32C_DP_2SRC,
  CRC32X_64C_DP_2SRC,
  CSEL_32_CONDSEL,
  CSEL_64_CONDSEL,
  CSETM_CSINV_32_CONDSEL,
  CSETM_CSINV_64_CONDSEL,
  CSET_CSINC_32_CONDSEL,
  CSET_CSINC_64_CONDSEL,
  CSINC_32_CONDSEL,
  CSINC_64_CONDSEL,
  CSINV_32_CONDSEL,
  CSINV_64_CONDSEL,
  CSNEG_32_CONDSEL,
  CSNEG_64_CONDSEL,
  DCPS1_DC_EXCEPTION,
  DCPS2_DC_EXCEPTION,
  DCPS3_DC_EXCEPTION,
  DC_SYS_CR_SYSTEM,
  DMB_BO_SYSTEM,
  DRPS_64E_BRANCH_REG,
  DSB_BO_SYSTEM,
  DUP_ASIMDINS_DR_R,
  DUP_ASIMDINS_DV_V,
  DUP_ASISDONE_ONLY,
  EON_32_LOG_SHIFT,
  EON_64_LOG_SHIFT,
  EOR_32_LOG_IMM,
  EOR_32_LOG_SHIFT,
  EOR_64_LOG_IMM,
  EOR_64_LOG_SHIFT,
  EOR_ASIMDSAME_ONLY,
  ERET_64E_BRANCH_REG,
  ESB_HI_SYSTEM,
  EXTR_32_EXTRACT,
  EXTR_64_EXTRACT,
  EXT_ASIMDEXT_ONLY,
  FABD_ASIMDSAME_ONLY,
  FABD_ASIMDSAMEFP16_ONLY,
  FABD_ASISDSAME_ONLY,
  FABD_ASISDSAMEFP16_ONLY,
  FABS_D_FLOATDP1,
  FABS_H_FLOATDP1,
  FABS_S_FLOATDP1,
  FABS_ASIMDMISC_R,
  FABS_ASIMDMISCFP16_R,
  FACGE_ASIMDSAME_ONLY,
  FACGE_ASIMDSAMEFP16_ONLY,
  FACGE_ASISDSAME_ONLY,
  FACGE_ASISDSAMEFP16_ONLY,
  FACGT_ASIMDSAME_ONLY,
  FACGT_ASIMDSAMEFP16_ONLY,
  FACGT_ASISDSAME_ONLY,
  FACGT_ASISDSAMEFP16_ONLY,
  FADDP_ASIMDSAME_ONLY,
  FADDP_ASIMDSAMEFP16_ONLY,
  FADDP_ASISDPAIR_ONLY_H,
  FADDP_ASISDPAIR_ONLY_SD,
  FADD_D_FLOATDP2,
  FADD_H_FLOATDP2,
  FADD_S_FLOATDP2,
  FADD_ASIMDSAME_ONLY,
  FADD_ASIMDSAMEFP16_ONLY,
  FCCMPE_D_FLOATCCMP,
  FCCMPE_H_FLOATCCMP,
  FCCMPE_S_FLOATCCMP,
  FCCMP_D_FLOATCCMP,
  FCCMP_H_FLOATCCMP,
  FCCMP_S_FLOATCCMP,
  FCMEQ_ASIMDMISC_FZ,
  FCMEQ_ASIMDMISCFP16_FZ,
  FCMEQ_ASIMDSAME_ONLY,
  FCMEQ_ASIMDSAMEFP16_ONLY,
  FCMEQ_ASISDMISC_FZ,
  FCMEQ_ASISDMISCFP16_FZ,
  FCMEQ_ASISDSAME_ONLY,
  FCMEQ_ASISDSAMEFP16_ONLY,
  FCMGE_ASIMDMISC_FZ,
  FCMGE_ASIMDMISCFP16_FZ,
  FCMGE_ASIMDSAME_ONLY,
  FCMGE_ASIMDSAMEFP16_ONLY,
  FCMGE_ASISDMISC_FZ,
  FCMGE_ASISDMISCFP16_FZ,
  FCMGE_ASISDSAME_ONLY,
  FCMGE_ASISDSAMEFP16_ONLY,
  FCMGT_ASIMDMISC_FZ,
  FCMGT_ASIMDMISCFP16_FZ,
  FCMGT_ASIMDSAME_ONLY,
  FCMGT_ASIMDSAMEFP16_ONLY,
  FCMGT_ASISDMISC_FZ,
  FCMGT_ASISDMISCFP16_FZ,
  FCMGT_ASISDSAME_ONLY,
  FCMGT_ASISDSAMEFP16_ONLY,
  FCMLE_ASIMDMISC_FZ,
  FCMLE_ASIMDMISCFP16_FZ,
  FCMLE_ASISDMISC_FZ,
  FCMLE_ASISDMISCFP16_FZ,
  FCMLT_ASIMDMISC_FZ,
  FCMLT_ASIMDMISCFP16_FZ,
  FCMLT_ASISDMISC_FZ,
  FCMLT_ASISDMISCFP16_FZ,
  FCMPE_DZ_FLOATCMP,
  FCMPE_D_FLOATCMP,
  FCMPE_HZ_FLOATCMP,
  FCMPE_H_FLOATCMP,
  FCMPE_SZ_FLOATCMP,
  FCMPE_S_FLOATCMP,
  FCMP_DZ_FLOATCMP,
  FCMP_D_FLOATCMP,
  FCMP_HZ_FLOATCMP,
  FCMP_H_FLOATCMP,
  FCMP_SZ_FLOATCMP,
  FCMP_S_FLOATCMP,
  FCSEL_D_FLOATSEL,
  FCSEL_H_FLOATSEL,
  FCSEL_S_FLOATSEL,
  FCVTAS_32D_FLOAT2INT,
  FCVTAS_32H_FLOAT2INT,
  FCVTAS_32S_FLOAT2INT,
  FCVTAS_64D_FLOAT2INT,
  FCVTAS_64H_FLOAT2INT,
  FCVTAS_64S_FLOAT2INT,
  FCVTAS_ASIMDMISC_R,
  FCVTAS_ASIMDMISCFP16_R,
  FCVTAS_ASISDMISC_R,
  FCVTAS_ASISDMISCFP16_R,
  FCVTAU_32D_FLOAT2INT,
  FCVTAU_32H_FLOAT2INT,
  FCVTAU_32S_FLOAT2INT,
  FCVTAU_64D_FLOAT2INT,
  FCVTAU_64H_FLOAT2INT,
  FCVTAU_64S_FLOAT2INT,
  FCVTAU_ASIMDMISC_R,
  FCVTAU_ASIMDMISCFP16_R,
  FCVTAU_ASISDMISC_R,
  FCVTAU_ASISDMISCFP16_R,
  FCVTL_ASIMDMISC_L,
  FCVTMS_32D_FLOAT2INT,
  FCVTMS_32H_FLOAT2INT,
  FCVTMS_32S_FLOAT2INT,
  FCVTMS_64D_FLOAT2INT,
  FCVTMS_64H_FLOAT2INT,
  FCVTMS_64S_FLOAT2INT,
  FCVTMS_ASIMDMISC_R,
  FCVTMS_ASIMDMISCFP16_R,
  FCVTMS_ASISDMISC_R,
  FCVTMS_ASISDMISCFP16_R,
  FCVTMU_32D_FLOAT2INT,
  FCVTMU_32H_FLOAT2INT,
  FCVTMU_32S_FLOAT2INT,
  FCVTMU_64D_FLOAT2INT,
  FCVTMU_64H_FLOAT2INT,
  FCVTMU_64S_FLOAT2INT,
  FCVTMU_ASIMDMISC_R,
  FCVTMU_ASIMDMISCFP16_R,
  FCVTMU_ASISDMISC_R,
  FCVTMU_ASISDMISCFP16_R,
  FCVTNS_32D_FLOAT2INT,
  FCVTNS_32H_FLOAT2INT,
  FCVTNS_32S_FLOAT2INT,
  FCVTNS_64D_FLOAT2INT,
  FCVTNS_64H_FLOAT2INT,
  FCVTNS_64S_FLOAT2INT,
  FCVTNS_ASIMDMISC_R,
  FCVTNS_ASIMDMISCFP16_R,
  FCVTNS_ASISDMISC_R,
  FCVTNS_ASISDMISCFP16_R,
  FCVTNU_32D_FLOAT2INT,
  FCVTNU_32H_FLOAT2INT,
  FCVTNU_32S_FLOAT2INT,
  FCVTNU_64D_FLOAT2INT,
  FCVTNU_64H_FLOAT2INT,
  FCVTNU_64S_FLOAT2INT,
  FCVTNU_ASIMDMISC_R,
  FCVTNU_ASIMDMISCFP16_R,
  FCVTNU_ASISDMISC_R,
  FCVTNU_ASISDMISCFP16_R,
  FCVTN_ASIMDMISC_N,
  FCVTPS_32D_FLOAT2INT,
  FCVTPS_32H_FLOAT2INT,
  FCVTPS_32S_FLOAT2INT,
  FCVTPS_64D_FLOAT2INT,
  FCVTPS_64H_FLOAT2INT,
  FCVTPS_64S_FLOAT2INT,
  FCVTPS_ASIMDMISC_R,
  FCVTPS_ASIMDMISCFP16_R,
  FCVTPS_ASISDMISC_R,
  FCVTPS_ASISDMISCFP16_R,
  FCVTPU_32D_FLOAT2INT,
  FCVTPU_32H_FLOAT2INT,
  FCVTPU_32S_FLOAT2INT,
  FCVTPU_64D_FLOAT2INT,
  FCVTPU_64H_FLOAT2INT,
  FCVTPU_64S_FLOAT2INT,
  FCVTPU_ASIMDMISC_R,
  FCVTPU_ASIMDMISCFP16_R,
  FCVTPU_ASISDMISC_R,
  FCVTPU_ASISDMISCFP16_R,
  FCVTXN_ASIMDMISC_N,
  FCVTXN_ASISDMISC_N,
  FCVTZS_32D_FLOAT2FIX,
  FCVTZS_32D_FLOAT2INT,
  FCVTZS_32H_FLOAT2FIX,
  FCVTZS_32H_FLOAT2INT,
  FCVTZS_32S_FLOAT2FIX,
  FCVTZS_32S_FLOAT2INT,
  FCVTZS_64D_FLOAT2FIX,
  FCVTZS_64D_FLOAT2INT,
  FCVTZS_64H_FLOAT2FIX,
  FCVTZS_64H_FLOAT2INT,
  FCVTZS_64S_FLOAT2FIX,
  FCVTZS_64S_FLOAT2INT,
  FCVTZS_ASIMDMISC_R,
  FCVTZS_ASIMDMISCFP16_R,
  FCVTZS_ASIMDSHF_C,
  FCVTZS_ASISDMISC_R,
  FCVTZS_ASISDMISCFP16_R,
  FCVTZS_ASISDSHF_C,
  FCVTZU_32D_FLOAT2FIX,
  FCVTZU_32D_FLOAT2INT,
  FCVTZU_32H_FLOAT2FIX,
  FCVTZU_32H_FLOAT2INT,
  FCVTZU_32S_FLOAT2FIX,
  FCVTZU_32S_FLOAT2INT,
  FCVTZU_64D_FLOAT2FIX,
  FCVTZU_64D_FLOAT2INT,
  FCVTZU_64H_FLOAT2FIX,
  FCVTZU_64H_FLOAT2INT,
  FCVTZU_64S_FLOAT2FIX,
  FCVTZU_64S_FLOAT2INT,
  FCVTZU_ASIMDMISC_R,
  FCVTZU_ASIMDMISCFP16_R,
  FCVTZU_ASIMDSHF_C,
  FCVTZU_ASISDMISC_R,
  FCVTZU_ASISDMISCFP16_R,
  FCVTZU_ASISDSHF_C,
  FCVT_DH_FLOATDP1,
  FCVT_DS_FLOATDP1,
  FCVT_HD_FLOATDP1,
  FCVT_HS_FLOATDP1,
  FCVT_SD_FLOATDP1,
  FCVT_SH_FLOATDP1,
  FDIV_D_FLOATDP2,
  FDIV_H_FLOATDP2,
  FDIV_S_FLOATDP2,
  FDIV_ASIMDSAME_ONLY,
  FDIV_ASIMDSAMEFP16_ONLY,
  FMADD_D_FLOATDP3,
  FMADD_H_FLOATDP3,
  FMADD_S_FLOATDP3,
  FMAXNMP_ASIMDSAME_ONLY,
  FMAXNMP_ASIMDSAMEFP16_ONLY,
  FMAXNMP_ASISDPAIR_ONLY_H,
  FMAXNMP_ASISDPAIR_ONLY_SD,
  FMAXNMV_ASIMDALL_ONLY_H,
  FMAXNMV_ASIMDALL_ONLY_SD,
  FMAXNM_D_FLOATDP2,
  FMAXNM_H_FLOATDP2,
  FMAXNM_S_FLOATDP2,
  FMAXNM_ASIMDSAME_ONLY,
  FMAXNM_ASIMDSAMEFP16_ONLY,
  FMAXP_ASIMDSAME_ONLY,
  FMAXP_ASIMDSAMEFP16_ONLY,
  FMAXP_ASISDPAIR_ONLY_H,
  FMAXP_ASISDPAIR_ONLY_SD,
  FMAXV_ASIMDALL_ONLY_H,
  FMAXV_ASIMDALL_ONLY_SD,
  FMAX_D_FLOATDP2,
  FMAX_H_FLOATDP2,
  FMAX_S_FLOATDP2,
  FMAX_ASIMDSAME_ONLY,
  FMAX_ASIMDSAMEFP16_ONLY,
  FMINNMP_ASIMDSAME_ONLY,
  FMINNMP_ASIMDSAMEFP16_ONLY,
  FMINNMP_ASISDPAIR_ONLY_H,
  FMINNMP_ASISDPAIR_ONLY_SD,
  FMINNMV_ASIMDALL_ONLY_H,
  FMINNMV_ASIMDALL_ONLY_SD,
  FMINNM_D_FLOATDP2,
  FMINNM_H_FLOATDP2,
  FMINNM_S_FLOATDP2,
  FMINNM_ASIMDSAME_ONLY,
  FMINNM_ASIMDSAMEFP16_ONLY,
  FMINP_ASIMDSAME_ONLY,
  FMINP_ASIMDSAMEFP16_ONLY,
  FMINP_ASISDPAIR_ONLY_H,
  FMINP_ASISDPAIR_ONLY_SD,
  FMINV_ASIMDALL_ONLY_H,
  FMINV_ASIMDALL_ONLY_SD,
  FMIN_D_FLOATDP2,
  FMIN_H_FLOATDP2,
  FMIN_S_FLOATDP2,
  FMIN_ASIMDSAME_ONLY,
  FMIN_ASIMDSAMEFP16_ONLY,
  FMLA_ASIMDELEM_RH_H,
  FMLA_ASIMDELEM_R_SD,
  FMLA_ASIMDSAME_ONLY,
  FMLA_ASIMDSAMEFP16_ONLY,
  FMLA_ASISDELEM_RH_H,
  FMLA_ASISDELEM_R_SD,
  FMLS_ASIMDELEM_RH_H,
  FMLS_ASIMDELEM_R_SD,
  FMLS_ASIMDSAME_ONLY,
  FMLS_ASIMDSAMEFP16_ONLY,
  FMLS_ASISDELEM_RH_H,
  FMLS_ASISDELEM_R_SD,
  FMOV_32H_FLOAT2INT,
  FMOV_32S_FLOAT2INT,
  FMOV_64D_FLOAT2INT,
  FMOV_64H_FLOAT2INT,
  FMOV_64VX_FLOAT2INT,
  FMOV_D64_FLOAT2INT,
  FMOV_D_FLOATDP1,
  FMOV_D_FLOATIMM,
  FMOV_H32_FLOAT2INT,
  FMOV_H64_FLOAT2INT,
  FMOV_H_FLOATDP1,
  FMOV_H_FLOATIMM,
  FMOV_S32_FLOAT2INT,
  FMOV_S_FLOATDP1,
  FMOV_S_FLOATIMM,
  FMOV_V64I_FLOAT2INT,
  FMOV_ASIMDIMM_D2_D,
  FMOV_ASIMDIMM_H_H,
  FMOV_ASIMDIMM_S_S,
  FMSUB_D_FLOATDP3,
  FMSUB_H_FLOATDP3,
  FMSUB_S_FLOATDP3,
  FMULX_ASIMDELEM_RH_H,
  FMULX_ASIMDELEM_R_SD,
  FMULX_ASIMDSAME_ONLY,
  FMULX_ASIMDSAMEFP16_ONLY,
  FMULX_ASISDELEM_RH_H,
  FMULX_ASISDELEM_R_SD,
  FMULX_ASISDSAME_ONLY,
  FMULX_ASISDSAMEFP16_ONLY,
  FMUL_D_FLOATDP2,
  FMUL_H_FLOATDP2,
  FMUL_S_FLOATDP2,
  FMUL_ASIMDELEM_RH_H,
  FMUL_ASIMDELEM_R_SD,
  FMUL_ASIMDSAME_ONLY,
  FMUL_ASIMDSAMEFP16_ONLY,
  FMUL_ASISDELEM_RH_H,
  FMUL_ASISDELEM_R_SD,
  FNEG_D_FLOATDP1,
  FNEG_H_FLOATDP1,
  FNEG_S_FLOATDP1,
  FNEG_ASIMDMISC_R,
  FNEG_ASIMDMISCFP16_R,
  FNMADD_D_FLOATDP3,
  FNMADD_H_FLOATDP3,
  FNMADD_S_FLOATDP3,
  FNMSUB_D_FLOATDP3,
  FNMSUB_H_FLOATDP3,
  FNMSUB_S_FLOATDP3,
  FNMUL_D_FLOATDP2,
  FNMUL_H_FLOATDP2,
  FNMUL_S_FLOATDP2,
  FRECPE_ASIMDMISC_R,
  FRECPE_ASIMDMISCFP16_R,
  FRECPE_ASISDMISC_R,
  FRECPE_ASISDMISCFP16_R,
  FRECPS_ASIMDSAME_ONLY,
  FRECPS_ASIMDSAMEFP16_ONLY,
  FRECPS_ASISDSAME_ONLY,
  FRECPS_ASISDSAMEFP16_ONLY,
  FRECPX_ASISDMISC_R,
  FRECPX_ASISDMISCFP16_R,
  FRINTA_D_FLOATDP1,
  FRINTA_H_FLOATDP1,
  FRINTA_S_FLOATDP1,
  FRINTA_ASIMDMISC_R,
  FRINTA_ASIMDMISCFP16_R,
  FRINTI_D_FLOATDP1,
  FRINTI_H_FLOATDP1,
  FRINTI_S_FLOATDP1,
  FRINTI_ASIMDMISC_R,
  FRINTI_ASIMDMISCFP16_R,
  FRINTM_D_FLOATDP1,
  FRINTM_H_FLOATDP1,
  FRINTM_S_FLOATDP1,
  FRINTM_ASIMDMISC_R,
  FRINTM_ASIMDMISCFP16_R,
  FRINTN_D_FLOATDP1,
  FRINTN_H_FLOATDP1,
  FRINTN_S_FLOATDP1,
  FRINTN_ASIMDMISC_R,
  FRINTN_ASIMDMISCFP16_R,
  FRINTP_D_FLOATDP1,
  FRINTP_H_FLOATDP1,
  FRINTP_S_FLOATDP1,
  FRINTP_ASIMDMISC_R,
  FRINTP_ASIMDMISCFP16_R,
  FRINTX_D_FLOATDP1,
  FRINTX_H_FLOATDP1,
  FRINTX_S_FLOATDP1,
  FRINTX_ASIMDMISC_R,
  FRINTX_ASIMDMISCFP16_R,
  FRINTZ_D_FLOATDP1,
  FRINTZ_H_FLOATDP1,
  FRINTZ_S_FLOATDP1,
  FRINTZ_ASIMDMISC_R,
  FRINTZ_ASIMDMISCFP16_R,
  FRSQRTE_ASIMDMISC_R,
  FRSQRTE_ASIMDMISCFP16_R,
  FRSQRTE_ASISDMISC_R,
  FRSQRTE_ASISDMISCFP16_R,
  FRSQRTS_ASIMDSAME_ONLY,
  FRSQRTS_ASIMDSAMEFP16_ONLY,
  FRSQRTS_ASISDSAME_ONLY,
  FRSQRTS_ASISDSAMEFP16_ONLY,
  FSQRT_D_FLOATDP1,
  FSQRT_H_FLOATDP1,
  FSQRT_S_FLOATDP1,
  FSQRT_ASIMDMISC_R,
  FSQRT_ASIMDMISCFP16_R,
  FSUB_D_FLOATDP2,
  FSUB_H_FLOATDP2,
  FSUB_S_FLOATDP2,
  FSUB_ASIMDSAME_ONLY,
  FSUB_ASIMDSAMEFP16_ONLY,
  HINT_1,
  HINT_2,
  HINT_3,
  HLT_EX_EXCEPTION,
  HVC_EX_EXCEPTION,
  IC_SYS_CR_SYSTEM,
  INS_ASIMDINS_IR_R,
  INS_ASIMDINS_IV_V,
  ISB_BI_SYSTEM,
  LD1R_ASISDLSO_R1,
  LD1R_ASISDLSOP_R1_I,
  LD1R_ASISDLSOP_RX1_R,
  LD1_ASISDLSE_R1_1V,
  LD1_ASISDLSE_R2_2V,
  LD1_ASISDLSE_R3_3V,
  LD1_ASISDLSE_R4_4V,
  LD1_ASISDLSEP_I1_I1,
  LD1_ASISDLSEP_I2_I2,
  LD1_ASISDLSEP_I3_I3,
  LD1_ASISDLSEP_I4_I4,
  LD1_ASISDLSEP_R1_R1,
  LD1_ASISDLSEP_R2_R2,
  LD1_ASISDLSEP_R3_R3,
  LD1_ASISDLSEP_R4_R4,
  LD1_ASISDLSO_B1_1B,
  LD1_ASISDLSO_D1_1D,
  LD1_ASISDLSO_H1_1H,
  LD1_ASISDLSO_S1_1S,
  LD1_ASISDLSOP_B1_I1B,
  LD1_ASISDLSOP_BX1_R1B,
  LD1_ASISDLSOP_D1_I1D,
  LD1_ASISDLSOP_DX1_R1D,
  LD1_ASISDLSOP_H1_I1H,
  LD1_ASISDLSOP_HX1_R1H,
  LD1_ASISDLSOP_S1_I1S,
  LD1_ASISDLSOP_SX1_R1S,
  LD2R_ASISDLSO_R2,
  LD2R_ASISDLSOP_R2_I,
  LD2R_ASISDLSOP_RX2_R,
  LD2_ASISDLSE_R2,
  LD2_ASISDLSEP_I2_I,
  LD2_ASISDLSEP_R2_R,
  LD2_ASISDLSO_B2_2B,
  LD2_ASISDLSO_D2_2D,
  LD2_ASISDLSO_H2_2H,
  LD2_ASISDLSO_S2_2S,
  LD2_ASISDLSOP_B2_I2B,
  LD2_ASISDLSOP_BX2_R2B,
  LD2_ASISDLSOP_D2_I2D,
  LD2_ASISDLSOP_DX2_R2D,
  LD2_ASISDLSOP_H2_I2H,
  LD2_ASISDLSOP_HX2_R2H,
  LD2_ASISDLSOP_S2_I2S,
  LD2_ASISDLSOP_SX2_R2S,
  LD3R_ASISDLSO_R3,
  LD3R_ASISDLSOP_R3_I,
  LD3R_ASISDLSOP_RX3_R,
  LD3_ASISDLSE_R3,
  LD3_ASISDLSEP_I3_I,
  LD3_ASISDLSEP_R3_R,
  LD3_ASISDLSO_B3_3B,
  LD3_ASISDLSO_D3_3D,
  LD3_ASISDLSO_H3_3H,
  LD3_ASISDLSO_S3_3S,
  LD3_ASISDLSOP_B3_I3B,
  LD3_ASISDLSOP_BX3_R3B,
  LD3_ASISDLSOP_D3_I3D,
  LD3_ASISDLSOP_DX3_R3D,
  LD3_ASISDLSOP_H3_I3H,
  LD3_ASISDLSOP_HX3_R3H,
  LD3_ASISDLSOP_S3_I3S,
  LD3_ASISDLSOP_SX3_R3S,
  LD4R_ASISDLSO_R4,
  LD4R_ASISDLSOP_R4_I,
  LD4R_ASISDLSOP_RX4_R,
  LD4_ASISDLSE_R4,
  LD4_ASISDLSEP_I4_I,
  LD4_ASISDLSEP_R4_R,
  LD4_ASISDLSO_B4_4B,
  LD4_ASISDLSO_D4_4D,
  LD4_ASISDLSO_H4_4H,
  LD4_ASISDLSO_S4_4S,
  LD4_ASISDLSOP_B4_I4B,
  LD4_ASISDLSOP_BX4_R4B,
  LD4_ASISDLSOP_D4_I4D,
  LD4_ASISDLSOP_DX4_R4D,
  LD4_ASISDLSOP_H4_I4H,
  LD4_ASISDLSOP_HX4_R4H,
  LD4_ASISDLSOP_S4_I4S,
  LD4_ASISDLSOP_SX4_R4S,
  LDADDAB_32_MEMOP,
  LDADDAH_32_MEMOP,
  LDADDALB_32_MEMOP,
  LDADDALH_32_MEMOP,
  LDADDAL_32_MEMOP,
  LDADDAL_64_MEMOP,
  LDADDA_32_MEMOP,
  LDADDA_64_MEMOP,
  LDADDB_32_MEMOP,
  LDADDH_32_MEMOP,
  LDADDLB_32_MEMOP,
  LDADDLH_32_MEMOP,
  LDADDL_32_MEMOP,
  LDADDL_64_MEMOP,
  LDADD_32_MEMOP,
  LDADD_64_MEMOP,
  LDARB_LR32_LDSTEXCL,
  LDARH_LR32_LDSTEXCL,
  LDAR_LR32_LDSTEXCL,
  LDAR_LR64_LDSTEXCL,
  LDAXP_LP32_LDSTEXCL,
  LDAXP_LP64_LDSTEXCL,
  LDAXRB_LR32_LDSTEXCL,
  LDAXRH_LR32_LDSTEXCL,
  LDAXR_LR32_LDSTEXCL,
  LDAXR_LR64_LDSTEXCL,
  LDCLRAB_32_MEMOP,
  LDCLRAH_32_MEMOP,
  LDCLRALB_32_MEMOP,
  LDCLRALH_32_MEMOP,
  LDCLRAL_32_MEMOP,
  LDCLRAL_64_MEMOP,
  LDCLRA_32_MEMOP,
  LDCLRA_64_MEMOP,
  LDCLRB_32_MEMOP,
  LDCLRH_32_MEMOP,
  LDCLRLB_32_MEMOP,
  LDCLRLH_32_MEMOP,
  LDCLRL_32_MEMOP,
  LDCLRL_64_MEMOP,
  LDCLR_32_MEMOP,
  LDCLR_64_MEMOP,
  LDEORAB_32_MEMOP,
  LDEORAH_32_MEMOP,
  LDEORALB_32_MEMOP,
  LDEORALH_32_MEMOP,
  LDEORAL_32_MEMOP,
  LDEORAL_64_MEMOP,
  LDEORA_32_MEMOP,
  LDEORA_64_MEMOP,
  LDEORB_32_MEMOP,
  LDEORH_32_MEMOP,
  LDEORLB_32_MEMOP,
  LDEORLH_32_MEMOP,
  LDEORL_32_MEMOP,
  LDEORL_64_MEMOP,
  LDEOR_32_MEMOP,
  LDEOR_64_MEMOP,
  LDLARB_LR32_LDSTEXCL,
  LDLARH_LR32_LDSTEXCL,
  LDLAR_LR32_LDSTEXCL,
  LDLAR_LR64_LDSTEXCL,
  LDNP_32_LDSTNAPAIR_OFFS,
  LDNP_64_LDSTNAPAIR_OFFS,
  LDNP_D_LDSTNAPAIR_OFFS,
  LDNP_Q_LDSTNAPAIR_OFFS,
  LDNP_S_LDSTNAPAIR_OFFS,
  LDPSW_64_LDSTPAIR_OFF,
  LDPSW_64_LDSTPAIR_POST,
  LDPSW_64_LDSTPAIR_PRE,
  LDP_32_LDSTPAIR_OFF,
  LDP_32_LDSTPAIR_POST,
  LDP_32_LDSTPAIR_PRE,
  LDP_64_LDSTPAIR_OFF,
  LDP_64_LDSTPAIR_POST,
  LDP_64_LDSTPAIR_PRE,
  LDP_D_LDSTPAIR_OFF,
  LDP_D_LDSTPAIR_POST,
  LDP_D_LDSTPAIR_PRE,
  LDP_Q_LDSTPAIR_OFF,
  LDP_Q_LDSTPAIR_POST,
  LDP_Q_LDSTPAIR_PRE,
  LDP_S_LDSTPAIR_OFF,
  LDP_S_LDSTPAIR_POST,
  LDP_S_LDSTPAIR_PRE,
  LDRB_32BL_LDST_REGOFF,
  LDRB_32B_LDST_REGOFF,
  LDRB_32_LDST_IMMPOST,
  LDRB_32_LDST_IMMPRE,
  LDRB_32_LDST_POS,
  LDRH_32_LDST_IMMPOST,
  LDRH_32_LDST_IMMPRE,
  LDRH_32_LDST_POS,
  LDRH_32_LDST_REGOFF,
  LDRSB_32BL_LDST_REGOFF,
  LDRSB_32B_LDST_REGOFF,
  LDRSB_32_LDST_IMMPOST,
  LDRSB_32_LDST_IMMPRE,
  LDRSB_32_LDST_POS,
  LDRSB_64BL_LDST_REGOFF,
  LDRSB_64B_LDST_REGOFF,
  LDRSB_64_LDST_IMMPOST,
  LDRSB_64_LDST_IMMPRE,
  LDRSB_64_LDST_POS,
  LDRSH_32_LDST_IMMPOST,
  LDRSH_32_LDST_IMMPRE,
  LDRSH_32_LDST_POS,
  LDRSH_32_LDST_REGOFF,
  LDRSH_64_LDST_IMMPOST,
  LDRSH_64_LDST_IMMPRE,
  LDRSH_64_LDST_POS,
  LDRSH_64_LDST_REGOFF,
  LDRSW_64_LDST_IMMPOST,
  LDRSW_64_LDST_IMMPRE,
  LDRSW_64_LDST_POS,
  LDRSW_64_LDST_REGOFF,
  LDRSW_64_LOADLIT,
  LDR_32_LDST_IMMPOST,
  LDR_32_LDST_IMMPRE,
  LDR_32_LDST_POS,
  LDR_32_LDST_REGOFF,
  LDR_32_LOADLIT,
  LDR_64_LDST_IMMPOST,
  LDR_64_LDST_IMMPRE,
  LDR_64_LDST_POS,
  LDR_64_LDST_REGOFF,
  LDR_64_LOADLIT,
  LDR_BL_LDST_REGOFF,
  LDR_B_LDST_IMMPOST,
  LDR_B_LDST_IMMPRE,
  LDR_B_LDST_POS,
  LDR_B_LDST_REGOFF,
  LDR_D_LDST_IMMPOST,
  LDR_D_LDST_IMMPRE,
  LDR_D_LDST_POS,
  LDR_D_LDST_REGOFF,
  LDR_D_LOADLIT,
  LDR_H_LDST_IMMPOST,
  LDR_H_LDST_IMMPRE,
  LDR_H_LDST_POS,
  LDR_H_LDST_REGOFF,
  LDR_Q_LDST_IMMPOST,
  LDR_Q_LDST_IMMPRE,
  LDR_Q_LDST_POS,
  LDR_Q_LDST_REGOFF,
  LDR_Q_LOADLIT,
  LDR_S_LDST_IMMPOST,
  LDR_S_LDST_IMMPRE,
  LDR_S_LDST_POS,
  LDR_S_LDST_REGOFF,
  LDR_S_LOADLIT,
  LDSETAB_32_MEMOP,
  LDSETAH_32_MEMOP,
  LDSETALB_32_MEMOP,
  LDSETALH_32_MEMOP,
  LDSETAL_32_MEMOP,
  LDSETAL_64_MEMOP,
  LDSETA_32_MEMOP,
  LDSETA_64_MEMOP,
  LDSETB_32_MEMOP,
  LDSETH_32_MEMOP,
  LDSETLB_32_MEMOP,
  LDSETLH_32_MEMOP,
  LDSETL_32_MEMOP,
  LDSETL_64_MEMOP,
  LDSET_32_MEMOP,
  LDSET_64_MEMOP,
  LDSMAXAB_32_MEMOP,
  LDSMAXAH_32_MEMOP,
  LDSMAXALB_32_MEMOP,
  LDSMAXALH_32_MEMOP,
  LDSMAXAL_32_MEMOP,
  LDSMAXAL_64_MEMOP,
  LDSMAXA_32_MEMOP,
  LDSMAXA_64_MEMOP,
  LDSMAXB_32_MEMOP,
  LDSMAXH_32_MEMOP,
  LDSMAXLB_32_MEMOP,
  LDSMAXLH_32_MEMOP,
  LDSMAXL_32_MEMOP,
  LDSMAXL_64_MEMOP,
  LDSMAX_32_MEMOP,
  LDSMAX_64_MEMOP,
  LDSMINAB_32_MEMOP,
  LDSMINAH_32_MEMOP,
  LDSMINALB_32_MEMOP,
  LDSMINALH_32_MEMOP,
  LDSMINAL_32_MEMOP,
  LDSMINAL_64_MEMOP,
  LDSMINA_32_MEMOP,
  LDSMINA_64_MEMOP,
  LDSMINB_32_MEMOP,
  LDSMINH_32_MEMOP,
  LDSMINLB_32_MEMOP,
  LDSMINLH_32_MEMOP,
  LDSMINL_32_MEMOP,
  LDSMINL_64_MEMOP,
  LDSMIN_32_MEMOP,
  LDSMIN_64_MEMOP,
  LDTRB_32_LDST_UNPRIV,
  LDTRH_32_LDST_UNPRIV,
  LDTRSB_32_LDST_UNPRIV,
  LDTRSB_64_LDST_UNPRIV,
  LDTRSH_32_LDST_UNPRIV,
  LDTRSH_64_LDST_UNPRIV,
  LDTRSW_64_LDST_UNPRIV,
  LDTR_32_LDST_UNPRIV,
  LDTR_64_LDST_UNPRIV,
  LDUMAXAB_32_MEMOP,
  LDUMAXAH_32_MEMOP,
  LDUMAXALB_32_MEMOP,
  LDUMAXALH_32_MEMOP,
  LDUMAXAL_32_MEMOP,
  LDUMAXAL_64_MEMOP,
  LDUMAXA_32_MEMOP,
  LDUMAXA_64_MEMOP,
  LDUMAXB_32_MEMOP,
  LDUMAXH_32_MEMOP,
  LDUMAXLB_32_MEMOP,
  LDUMAXLH_32_MEMOP,
  LDUMAXL_32_MEMOP,
  LDUMAXL_64_MEMOP,
  LDUMAX_32_MEMOP,
  LDUMAX_64_MEMOP,
  LDUMINAB_32_MEMOP,
  LDUMINAH_32_MEMOP,
  LDUMINALB_32_MEMOP,
  LDUMINALH_32_MEMOP,
  LDUMINAL_32_MEMOP,
  LDUMINAL_64_MEMOP,
  LDUMINA_32_MEMOP,
  LDUMINA_64_MEMOP,
  LDUMINB_32_MEMOP,
  LDUMINH_32_MEMOP,
  LDUMINLB_32_MEMOP,
  LDUMINLH_32_MEMOP,
  LDUMINL_32_MEMOP,
  LDUMINL_64_MEMOP,
  LDUMIN_32_MEMOP,
  LDUMIN_64_MEMOP,
  LDURB_32_LDST_UNSCALED,
  LDURH_32_LDST_UNSCALED,
  LDURSB_32_LDST_UNSCALED,
  LDURSB_64_LDST_UNSCALED,
  LDURSH_32_LDST_UNSCALED,
  LDURSH_64_LDST_UNSCALED,
  LDURSW_64_LDST_UNSCALED,
  LDUR_32_LDST_UNSCALED,
  LDUR_64_LDST_UNSCALED,
  LDUR_B_LDST_UNSCALED,
  LDUR_D_LDST_UNSCALED,
  LDUR_H_LDST_UNSCALED,
  LDUR_Q_LDST_UNSCALED,
  LDUR_S_LDST_UNSCALED,
  LDXP_LP32_LDSTEXCL,
  LDXP_LP64_LDSTEXCL,
  LDXRB_LR32_LDSTEXCL,
  LDXRH_LR32_LDSTEXCL,
  LDXR_LR32_LDSTEXCL,
  LDXR_LR64_LDSTEXCL,
  LSLV_32_DP_2SRC,
  LSLV_64_DP_2SRC,
  LSL_LSLV_32_DP_2SRC,
  LSL_LSLV_64_DP_2SRC,
  LSL_UBFM_32M_BITFIELD,
  LSL_UBFM_64M_BITFIELD,
  LSRV_32_DP_2SRC,
  LSRV_64_DP_2SRC,
  LSR_LSRV_32_DP_2SRC,
  LSR_LSRV_64_DP_2SRC,
  LSR_UBFM_32M_BITFIELD,
  LSR_UBFM_64M_BITFIELD,
  MADD_32A_DP_3SRC,
  MADD_64A_DP_3SRC,
  MLA_ASIMDELEM_R,
  MLA_ASIMDSAME_ONLY,
  MLS_ASIMDELEM_R,
  MLS_ASIMDSAME_ONLY,
  MNEG_MSUB_32A_DP_3SRC,
  MNEG_MSUB_64A_DP_3SRC,
  MOVI_ASIMDIMM_D2_D,
  MOVI_ASIMDIMM_D_DS,
  MOVI_ASIMDIMM_L_HL,
  MOVI_ASIMDIMM_L_SL,
  MOVI_ASIMDIMM_M_SM,
  MOVI_ASIMDIMM_N_B,
  MOVK_32_MOVEWIDE,
  MOVK_64_MOVEWIDE,
  MOVN_32_MOVEWIDE,
  MOVN_64_MOVEWIDE,
  MOVZ_32_MOVEWIDE,
  MOVZ_64_MOVEWIDE,
  MOV_ADD_32_ADDSUB_IMM,
  MOV_ADD_64_ADDSUB_IMM,
  MOV_DUP_ASISDONE_ONLY,
  MOV_INS_ASIMDINS_IR_R,
  MOV_INS_ASIMDINS_IV_V,
  MOV_MOVN_32_MOVEWIDE,
  MOV_MOVN_64_MOVEWIDE,
  MOV_MOVZ_32_MOVEWIDE,
  MOV_MOVZ_64_MOVEWIDE,
  MOV_ORR_32_LOG_IMM,
  MOV_ORR_32_LOG_SHIFT,
  MOV_ORR_64_LOG_IMM,
  MOV_ORR_64_LOG_SHIFT,
  MOV_ORR_ASIMDSAME_ONLY,
  MOV_UMOV_ASIMDINS_W_W,
  MOV_UMOV_ASIMDINS_X_X,
  MRS_RS_SYSTEM,
  MSR_SI_SYSTEM,
  MSR_SR_SYSTEM,
  MSUB_32A_DP_3SRC,
  MSUB_64A_DP_3SRC,
  MUL_MADD_32A_DP_3SRC,
  MUL_MADD_64A_DP_3SRC,
  MUL_ASIMDELEM_R,
  MUL_ASIMDSAME_ONLY,
  MVNI_ASIMDIMM_L_HL,
  MVNI_ASIMDIMM_L_SL,
  MVNI_ASIMDIMM_M_SM,
  MVN_NOT_ASIMDMISC_R,
  MVN_ORN_32_LOG_SHIFT,
  MVN_ORN_64_LOG_SHIFT,
  NEGS_SUBS_32_ADDSUB_SHIFT,
  NEGS_SUBS_64_ADDSUB_SHIFT,
  NEG_SUB_32_ADDSUB_SHIFT,
  NEG_SUB_64_ADDSUB_SHIFT,
  NEG_ASIMDMISC_R,
  NEG_ASISDMISC_R,
  NGCS_SBCS_32_ADDSUB_CARRY,
  NGCS_SBCS_64_ADDSUB_CARRY,
  NGC_SBC_32_ADDSUB_CARRY,
  NGC_SBC_64_ADDSUB_CARRY,
  NOP_HI_SYSTEM,
  NOT_ASIMDMISC_R,
  ORN_32_LOG_SHIFT,
  ORN_64_LOG_SHIFT,
  ORN_ASIMDSAME_ONLY,
  ORR_32_LOG_IMM,
  ORR_32_LOG_SHIFT,
  ORR_64_LOG_IMM,
  ORR_64_LOG_SHIFT,
  ORR_ASIMDIMM_L_HL,
  ORR_ASIMDIMM_L_SL,
  ORR_ASIMDSAME_ONLY,
  PMULL_ASIMDDIFF_L,
  PMUL_ASIMDSAME_ONLY,
  PRFM_P_LDST_POS,
  PRFM_P_LDST_REGOFF,
  PRFM_P_LOADLIT,
  PRFUM_P_LDST_UNSCALED,
  PSB_HC_SYSTEM,
  RADDHN_ASIMDDIFF_N,
  RBIT_32_DP_1SRC,
  RBIT_64_DP_1SRC,
  RBIT_ASIMDMISC_R,
  RET_64R_BRANCH_REG,
  REV16_32_DP_1SRC,
  REV16_64_DP_1SRC,
  REV16_ASIMDMISC_R,
  REV32_64_DP_1SRC,
  REV32_ASIMDMISC_R,
  REV64_REV_64_DP_1SRC,
  REV64_ASIMDMISC_R,
  REV_32_DP_1SRC,
  REV_64_DP_1SRC,
  RORV_32_DP_2SRC,
  RORV_64_DP_2SRC,
  ROR_EXTR_32_EXTRACT,
  ROR_EXTR_64_EXTRACT,
  ROR_RORV_32_DP_2SRC,
  ROR_RORV_64_DP_2SRC,
  RSHRN_ASIMDSHF_N,
  RSUBHN_ASIMDDIFF_N,
  SABAL_ASIMDDIFF_L,
  SABA_ASIMDSAME_ONLY,
  SABDL_ASIMDDIFF_L,
  SABD_ASIMDSAME_ONLY,
  SADALP_ASIMDMISC_P,
  SADDLP_ASIMDMISC_P,
  SADDLV_ASIMDALL_ONLY,
  SADDL_ASIMDDIFF_L,
  SADDW_ASIMDDIFF_W,
  SBCS_32_ADDSUB_CARRY,
  SBCS_64_ADDSUB_CARRY,
  SBC_32_ADDSUB_CARRY,
  SBC_64_ADDSUB_CARRY,
  SBFIZ_SBFM_32M_BITFIELD,
  SBFIZ_SBFM_64M_BITFIELD,
  SBFM_32M_BITFIELD,
  SBFM_64M_BITFIELD,
  SBFX_SBFM_32M_BITFIELD,
  SBFX_SBFM_64M_BITFIELD,
  SCVTF_D32_FLOAT2FIX,
  SCVTF_D32_FLOAT2INT,
  SCVTF_D64_FLOAT2FIX,
  SCVTF_D64_FLOAT2INT,
  SCVTF_H32_FLOAT2FIX,
  SCVTF_H32_FLOAT2INT,
  SCVTF_H64_FLOAT2FIX,
  SCVTF_H64_FLOAT2INT,
  SCVTF_S32_FLOAT2FIX,
  SCVTF_S32_FLOAT2INT,
  SCVTF_S64_FLOAT2FIX,
  SCVTF_S64_FLOAT2INT,
  SCVTF_ASIMDMISC_R,
  SCVTF_ASIMDMISCFP16_R,
  SCVTF_ASIMDSHF_C,
  SCVTF_ASISDMISC_R,
  SCVTF_ASISDMISCFP16_R,
  SCVTF_ASISDSHF_C,
  SDIV_32_DP_2SRC,
  SDIV_64_DP_2SRC,
  SEVL_HI_SYSTEM,
  SEV_HI_SYSTEM,
  SHA1C_QSV_CRYPTOSHA3,
  SHA1H_SS_CRYPTOSHA2,
  SHA1M_QSV_CRYPTOSHA3,
  SHA1P_QSV_CRYPTOSHA3,
  SHA1SU0_VVV_CRYPTOSHA3,
  SHA1SU1_VV_CRYPTOSHA2,
  SHA256H2_QQV_CRYPTOSHA3,
  SHA256H_QQV_CRYPTOSHA3,
  SHA256SU0_VV_CRYPTOSHA2,
  SHA256SU1_VVV_CRYPTOSHA3,
  SHADD_ASIMDSAME_ONLY,
  SHLL_ASIMDMISC_S,
  SHL_ASIMDSHF_R,
  SHL_ASISDSHF_R,
  SHRN_ASIMDSHF_N,
  SHSUB_ASIMDSAME_ONLY,
  SLI_ASIMDSHF_R,
  SLI_ASISDSHF_R,
  SMADDL_64WA_DP_3SRC,
  SMAXP_ASIMDSAME_ONLY,
  SMAXV_ASIMDALL_ONLY,
  SMAX_ASIMDSAME_ONLY,
  SMC_EX_EXCEPTION,
  SMINP_ASIMDSAME_ONLY,
  SMINV_ASIMDALL_ONLY,
  SMIN_ASIMDSAME_ONLY,
  SMLAL_ASIMDDIFF_L,
  SMLAL_ASIMDELEM_L,
  SMLSL_ASIMDDIFF_L,
  SMLSL_ASIMDELEM_L,
  SMNEGL_SMSUBL_64WA_DP_3SRC,
  SMOV_ASIMDINS_W_W,
  SMOV_ASIMDINS_X_X,
  SMSUBL_64WA_DP_3SRC,
  SMULH_64_DP_3SRC,
  SMULL_SMADDL_64WA_DP_3SRC,
  SMULL_ASIMDDIFF_L,
  SMULL_ASIMDELEM_L,
  SQABS_ASIMDMISC_R,
  SQABS_ASISDMISC_R,
  SQADD_ASIMDSAME_ONLY,
  SQADD_ASISDSAME_ONLY,
  SQDMLAL_ASIMDDIFF_L,
  SQDMLAL_ASIMDELEM_L,
  SQDMLAL_ASISDDIFF_ONLY,
  SQDMLAL_ASISDELEM_L,
  SQDMLSL_ASIMDDIFF_L,
  SQDMLSL_ASIMDELEM_L,
  SQDMLSL_ASISDDIFF_ONLY,
  SQDMLSL_ASISDELEM_L,
  SQDMULH_ASIMDELEM_R,
  SQDMULH_ASIMDSAME_ONLY,
  SQDMULH_ASISDELEM_R,
  SQDMULH_ASISDSAME_ONLY,
  SQDMULL_ASIMDDIFF_L,
  SQDMULL_ASIMDELEM_L,
  SQDMULL_ASISDDIFF_ONLY,
  SQDMULL_ASISDELEM_L,
  SQNEG_ASIMDMISC_R,
  SQNEG_ASISDMISC_R,
  SQRDMLAH_ASIMDELEM_R,
  SQRDMLAH_ASIMDSAME2_ONLY,
  SQRDMLAH_ASISDELEM_R,
  SQRDMLAH_ASISDSAME2_ONLY,
  SQRDMLSH_ASIMDELEM_R,
  SQRDMLSH_ASIMDSAME2_ONLY,
  SQRDMLSH_ASISDELEM_R,
  SQRDMLSH_ASISDSAME2_ONLY,
  SQRDMULH_ASIMDELEM_R,
  SQRDMULH_ASIMDSAME_ONLY,
  SQRDMULH_ASISDELEM_R,
  SQRDMULH_ASISDSAME_ONLY,
  SQRSHL_ASIMDSAME_ONLY,
  SQRSHL_ASISDSAME_ONLY,
  SQRSHRN_ASIMDSHF_N,
  SQRSHRN_ASISDSHF_N,
  SQRSHRUN_ASIMDSHF_N,
  SQRSHRUN_ASISDSHF_N,
  SQSHLU_ASIMDSHF_R,
  SQSHLU_ASISDSHF_R,
  SQSHL_ASIMDSAME_ONLY,
  SQSHL_ASIMDSHF_R,
  SQSHL_ASISDSAME_ONLY,
  SQSHL_ASISDSHF_R,
  SQSHRN_ASIMDSHF_N,
  SQSHRN_ASISDSHF_N,
  SQSHRUN_ASIMDSHF_N,
  SQSHRUN_ASISDSHF_N,
  SQSUB_ASIMDSAME_ONLY,
  SQSUB_ASISDSAME_ONLY,
  SQXTN_ASIMDMISC_N,
  SQXTN_ASISDMISC_N,
  SQXTUN_ASIMDMISC_N,
  SQXTUN_ASISDMISC_N,
  SRHADD_ASIMDSAME_ONLY,
  SRI_ASIMDSHF_R,
  SRI_ASISDSHF_R,
  SRSHL_ASIMDSAME_ONLY,
  SRSHL_ASISDSAME_ONLY,
  SRSHR_ASIMDSHF_R,
  SRSHR_ASISDSHF_R,
  SRSRA_ASIMDSHF_R,
  SRSRA_ASISDSHF_R,
  SSHLL_ASIMDSHF_L,
  SSHL_ASIMDSAME_ONLY,
  SSHL_ASISDSAME_ONLY,
  SSHR_ASIMDSHF_R,
  SSHR_ASISDSHF_R,
  SSRA_ASIMDSHF_R,
  SSRA_ASISDSHF_R,
  SSUBL_ASIMDDIFF_L,
  SSUBW_ASIMDDIFF_W,
  ST1_ASISDLSE_R1_1V,
  ST1_ASISDLSE_R2_2V,
  ST1_ASISDLSE_R3_3V,
  ST1_ASISDLSE_R4_4V,
  ST1_ASISDLSEP_I1_I1,
  ST1_ASISDLSEP_I2_I2,
  ST1_ASISDLSEP_I3_I3,
  ST1_ASISDLSEP_I4_I4,
  ST1_ASISDLSEP_R1_R1,
  ST1_ASISDLSEP_R2_R2,
  ST1_ASISDLSEP_R3_R3,
  ST1_ASISDLSEP_R4_R4,
  ST1_ASISDLSO_B1_1B,
  ST1_ASISDLSO_D1_1D,
  ST1_ASISDLSO_H1_1H,
  ST1_ASISDLSO_S1_1S,
  ST1_ASISDLSOP_B1_I1B,
  ST1_ASISDLSOP_BX1_R1B,
  ST1_ASISDLSOP_D1_I1D,
  ST1_ASISDLSOP_DX1_R1D,
  ST1_ASISDLSOP_H1_I1H,
  ST1_ASISDLSOP_HX1_R1H,
  ST1_ASISDLSOP_S1_I1S,
  ST1_ASISDLSOP_SX1_R1S,
  ST2_ASISDLSE_R2,
  ST2_ASISDLSEP_I2_I,
  ST2_ASISDLSEP_R2_R,
  ST2_ASISDLSO_B2_2B,
  ST2_ASISDLSO_D2_2D,
  ST2_ASISDLSO_H2_2H,
  ST2_ASISDLSO_S2_2S,
  ST2_ASISDLSOP_B2_I2B,
  ST2_ASISDLSOP_BX2_R2B,
  ST2_ASISDLSOP_D2_I2D,
  ST2_ASISDLSOP_DX2_R2D,
  ST2_ASISDLSOP_H2_I2H,
  ST2_ASISDLSOP_HX2_R2H,
  ST2_ASISDLSOP_S2_I2S,
  ST2_ASISDLSOP_SX2_R2S,
  ST3_ASISDLSE_R3,
  ST3_ASISDLSEP_I3_I,
  ST3_ASISDLSEP_R3_R,
  ST3_ASISDLSO_B3_3B,
  ST3_ASISDLSO_D3_3D,
  ST3_ASISDLSO_H3_3H,
  ST3_ASISDLSO_S3_3S,
  ST3_ASISDLSOP_B3_I3B,
  ST3_ASISDLSOP_BX3_R3B,
  ST3_ASISDLSOP_D3_I3D,
  ST3_ASISDLSOP_DX3_R3D,
  ST3_ASISDLSOP_H3_I3H,
  ST3_ASISDLSOP_HX3_R3H,
  ST3_ASISDLSOP_S3_I3S,
  ST3_ASISDLSOP_SX3_R3S,
  ST4_ASISDLSE_R4,
  ST4_ASISDLSEP_I4_I,
  ST4_ASISDLSEP_R4_R,
  ST4_ASISDLSO_B4_4B,
  ST4_ASISDLSO_D4_4D,
  ST4_ASISDLSO_H4_4H,
  ST4_ASISDLSO_S4_4S,
  ST4_ASISDLSOP_B4_I4B,
  ST4_ASISDLSOP_BX4_R4B,
  ST4_ASISDLSOP_D4_I4D,
  ST4_ASISDLSOP_DX4_R4D,
  ST4_ASISDLSOP_H4_I4H,
  ST4_ASISDLSOP_HX4_R4H,
  ST4_ASISDLSOP_S4_I4S,
  ST4_ASISDLSOP_SX4_R4S,
  STADDB_32S_MEMOP,
  STADDH_32S_MEMOP,
  STADDLB_32S_MEMOP,
  STADDLH_32S_MEMOP,
  STADDL_32S_MEMOP,
  STADDL_64S_MEMOP,
  STADD_32S_MEMOP,
  STADD_64S_MEMOP,
  STCLRB_32S_MEMOP,
  STCLRH_32S_MEMOP,
  STCLRLB_32S_MEMOP,
  STCLRLH_32S_MEMOP,
  STCLRL_32S_MEMOP,
  STCLRL_64S_MEMOP,
  STCLR_32S_MEMOP,
  STCLR_64S_MEMOP,
  STEORB_32S_MEMOP,
  STEORH_32S_MEMOP,
  STEORLB_32S_MEMOP,
  STEORLH_32S_MEMOP,
  STEORL_32S_MEMOP,
  STEORL_64S_MEMOP,
  STEOR_32S_MEMOP,
  STEOR_64S_MEMOP,
  STLLRB_SL32_LDSTEXCL,
  STLLRH_SL32_LDSTEXCL,
  STLLR_SL32_LDSTEXCL,
  STLLR_SL64_LDSTEXCL,
  STLRB_SL32_LDSTEXCL,
  STLRH_SL32_LDSTEXCL,
  STLR_SL32_LDSTEXCL,
  STLR_SL64_LDSTEXCL,
  STLXP_SP32_LDSTEXCL,
  STLXP_SP64_LDSTEXCL,
  STLXRB_SR32_LDSTEXCL,
  STLXRH_SR32_LDSTEXCL,
  STLXR_SR32_LDSTEXCL,
  STLXR_SR64_LDSTEXCL,
  STNP_32_LDSTNAPAIR_OFFS,
  STNP_64_LDSTNAPAIR_OFFS,
  STNP_D_LDSTNAPAIR_OFFS,
  STNP_Q_LDSTNAPAIR_OFFS,
  STNP_S_LDSTNAPAIR_OFFS,
  STP_32_LDSTPAIR_OFF,
  STP_32_LDSTPAIR_POST,
  STP_32_LDSTPAIR_PRE,
  STP_64_LDSTPAIR_OFF,
  STP_64_LDSTPAIR_POST,
  STP_64_LDSTPAIR_PRE,
  STP_D_LDSTPAIR_OFF,
  STP_D_LDSTPAIR_POST,
  STP_D_LDSTPAIR_PRE,
  STP_Q_LDSTPAIR_OFF,
  STP_Q_LDSTPAIR_POST,
  STP_Q_LDSTPAIR_PRE,
  STP_S_LDSTPAIR_OFF,
  STP_S_LDSTPAIR_POST,
  STP_S_LDSTPAIR_PRE,
  STRB_32BL_LDST_REGOFF,
  STRB_32B_LDST_REGOFF,
  STRB_32_LDST_IMMPOST,
  STRB_32_LDST_IMMPRE,
  STRB_32_LDST_POS,
  STRH_32_LDST_IMMPOST,
  STRH_32_LDST_IMMPRE,
  STRH_32_LDST_POS,
  STRH_32_LDST_REGOFF,
  STR_32_LDST_IMMPOST,
  STR_32_LDST_IMMPRE,
  STR_32_LDST_POS,
  STR_32_LDST_REGOFF,
  STR_64_LDST_IMMPOST,
  STR_64_LDST_IMMPRE,
  STR_64_LDST_POS,
  STR_64_LDST_REGOFF,
  STR_BL_LDST_REGOFF,
  STR_B_LDST_IMMPOST,
  STR_B_LDST_IMMPRE,
  STR_B_LDST_POS,
  STR_B_LDST_REGOFF,
  STR_D_LDST_IMMPOST,
  STR_D_LDST_IMMPRE,
  STR_D_LDST_POS,
  STR_D_LDST_REGOFF,
  STR_H_LDST_IMMPOST,
  STR_H_LDST_IMMPRE,
  STR_H_LDST_POS,
  STR_H_LDST_REGOFF,
  STR_Q_LDST_IMMPOST,
  STR_Q_LDST_IMMPRE,
  STR_Q_LDST_POS,
  STR_Q_LDST_REGOFF,
  STR_S_LDST_IMMPOST,
  STR_S_LDST_IMMPRE,
  STR_S_LDST_POS,
  STR_S_LDST_REGOFF,
  STSETB_32S_MEMOP,
  STSETH_32S_MEMOP,
  STSETLB_32S_MEMOP,
  STSETLH_32S_MEMOP,
  STSETL_32S_MEMOP,
  STSETL_64S_MEMOP,
  STSET_32S_MEMOP,
  STSET_64S_MEMOP,
  STSMAXB_32S_MEMOP,
  STSMAXH_32S_MEMOP,
  STSMAXLB_32S_MEMOP,
  STSMAXLH_32S_MEMOP,
  STSMAXL_32S_MEMOP,
  STSMAXL_64S_MEMOP,
  STSMAX_32S_MEMOP,
  STSMAX_64S_MEMOP,
  STSMINB_32S_MEMOP,
  STSMINH_32S_MEMOP,
  STSMINLB_32S_MEMOP,
  STSMINLH_32S_MEMOP,
  STSMINL_32S_MEMOP,
  STSMINL_64S_MEMOP,
  STSMIN_32S_MEMOP,
  STSMIN_64S_MEMOP,
  STTRB_32_LDST_UNPRIV,
  STTRH_32_LDST_UNPRIV,
  STTR_32_LDST_UNPRIV,
  STTR_64_LDST_UNPRIV,
  STUMAXB_32S_MEMOP,
  STUMAXH_32S_MEMOP,
  STUMAXLB_32S_MEMOP,
  STUMAXLH_32S_MEMOP,
  STUMAXL_32S_MEMOP,
  STUMAXL_64S_MEMOP,
  STUMAX_32S_MEMOP,
  STUMAX_64S_MEMOP,
  STUMINB_32S_MEMOP,
  STUMINH_32S_MEMOP,
  STUMINLB_32S_MEMOP,
  STUMINLH_32S_MEMOP,
  STUMINL_32S_MEMOP,
  STUMINL_64S_MEMOP,
  STUMIN_32S_MEMOP,
  STUMIN_64S_MEMOP,
  STURB_32_LDST_UNSCALED,
  STURH_32_LDST_UNSCALED,
  STUR_32_LDST_UNSCALED,
  STUR_64_LDST_UNSCALED,
  STUR_B_LDST_UNSCALED,
  STUR_D_LDST_UNSCALED,
  STUR_H_LDST_UNSCALED,
  STUR_Q_LDST_UNSCALED,
  STUR_S_LDST_UNSCALED,
  STXP_SP32_LDSTEXCL,
  STXP_SP64_LDSTEXCL,
  STXRB_SR32_LDSTEXCL,
  STXRH_SR32_LDSTEXCL,
  STXR_SR32_LDSTEXCL,
  STXR_SR64_LDSTEXCL,
  SUBHN_ASIMDDIFF_N,
  SUBS_32S_ADDSUB_EXT,
  SUBS_32S_ADDSUB_IMM,
  SUBS_32_ADDSUB_SHIFT,
  SUBS_64S_ADDSUB_EXT,
  SUBS_64S_ADDSUB_IMM,
  SUBS_64_ADDSUB_SHIFT,
  SUB_32_ADDSUB_EXT,
  SUB_32_ADDSUB_IMM,
  SUB_32_ADDSUB_SHIFT,
  SUB_64_ADDSUB_EXT,
  SUB_64_ADDSUB_IMM,
  SUB_64_ADDSUB_SHIFT,
  SUB_ASIMDSAME_ONLY,
  SUB_ASISDSAME_ONLY,
  SUQADD_ASIMDMISC_R,
  SUQADD_ASISDMISC_R,
  SVC_EX_EXCEPTION,
  SWPAB_32_MEMOP,
  SWPAH_32_MEMOP,
  SWPALB_32_MEMOP,
  SWPALH_32_MEMOP,
  SWPAL_32_MEMOP,
  SWPAL_64_MEMOP,
  SWPA_32_MEMOP,
  SWPA_64_MEMOP,
  SWPB_32_MEMOP,
  SWPH_32_MEMOP,
  SWPLB_32_MEMOP,
  SWPLH_32_MEMOP,
  SWPL_32_MEMOP,
  SWPL_64_MEMOP,
  SWP_32_MEMOP,
  SWP_64_MEMOP,
  SXTB_SBFM_32M_BITFIELD,
  SXTB_SBFM_64M_BITFIELD,
  SXTH_SBFM_32M_BITFIELD,
  SXTH_SBFM_64M_BITFIELD,
  SXTL_SSHLL_ASIMDSHF_L,
  SXTW_SBFM_64M_BITFIELD,
  SYSL_RC_SYSTEM,
  SYS_CR_SYSTEM,
  TBL_ASIMDTBL_L1_1,
  TBL_ASIMDTBL_L2_2,
  TBL_ASIMDTBL_L3_3,
  TBL_ASIMDTBL_L4_4,
  TBNZ_ONLY_TESTBRANCH,
  TBX_ASIMDTBL_L1_1,
  TBX_ASIMDTBL_L2_2,
  TBX_ASIMDTBL_L3_3,
  TBX_ASIMDTBL_L4_4,
  TBZ_ONLY_TESTBRANCH,
  TLBI_SYS_CR_SYSTEM,
  TRN1_ASIMDPERM_ONLY,
  TRN2_ASIMDPERM_ONLY,
  TST_ANDS_32S_LOG_IMM,
  TST_ANDS_32_LOG_SHIFT,
  TST_ANDS_64S_LOG_IMM,
  TST_ANDS_64_LOG_SHIFT,
  UABAL_ASIMDDIFF_L,
  UABA_ASIMDSAME_ONLY,
  UABDL_ASIMDDIFF_L,
  UABD_ASIMDSAME_ONLY,
  UADALP_ASIMDMISC_P,
  UADDLP_ASIMDMISC_P,
  UADDLV_ASIMDALL_ONLY,
  UADDL_ASIMDDIFF_L,
  UADDW_ASIMDDIFF_W,
  UBFIZ_UBFM_32M_BITFIELD,
  UBFIZ_UBFM_64M_BITFIELD,
  UBFM_32M_BITFIELD,
  UBFM_64M_BITFIELD,
  UBFX_UBFM_32M_BITFIELD,
  UBFX_UBFM_64M_BITFIELD,
  UCVTF_D32_FLOAT2FIX,
  UCVTF_D32_FLOAT2INT,
  UCVTF_D64_FLOAT2FIX,
  UCVTF_D64_FLOAT2INT,
  UCVTF_H32_FLOAT2FIX,
  UCVTF_H32_FLOAT2INT,
  UCVTF_H64_FLOAT2FIX,
  UCVTF_H64_FLOAT2INT,
  UCVTF_S32_FLOAT2FIX,
  UCVTF_S32_FLOAT2INT,
  UCVTF_S64_FLOAT2FIX,
  UCVTF_S64_FLOAT2INT,
  UCVTF_ASIMDMISC_R,
  UCVTF_ASIMDMISCFP16_R,
  UCVTF_ASIMDSHF_C,
  UCVTF_ASISDMISC_R,
  UCVTF_ASISDMISCFP16_R,
  UCVTF_ASISDSHF_C,
  UDIV_32_DP_2SRC,
  UDIV_64_DP_2SRC,
  UHADD_ASIMDSAME_ONLY,
  UHSUB_ASIMDSAME_ONLY,
  UMADDL_64WA_DP_3SRC,
  UMAXP_ASIMDSAME_ONLY,
  UMAXV_ASIMDALL_ONLY,
  UMAX_ASIMDSAME_ONLY,
  UMINP_ASIMDSAME_ONLY,
  UMINV_ASIMDALL_ONLY,
  UMIN_ASIMDSAME_ONLY,
  UMLAL_ASIMDDIFF_L,
  UMLAL_ASIMDELEM_L,
  UMLSL_ASIMDDIFF_L,
  UMLSL_ASIMDELEM_L,
  UMNEGL_UMSUBL_64WA_DP_3SRC,
  UMOV_ASIMDINS_W_W,
  UMOV_ASIMDINS_X_X,
  UMSUBL_64WA_DP_3SRC,
  UMULH_64_DP_3SRC,
  UMULL_UMADDL_64WA_DP_3SRC,
  UMULL_ASIMDDIFF_L,
  UMULL_ASIMDELEM_L,
  UQADD_ASIMDSAME_ONLY,
  UQADD_ASISDSAME_ONLY,
  UQRSHL_ASIMDSAME_ONLY,
  UQRSHL_ASISDSAME_ONLY,
  UQRSHRN_ASIMDSHF_N,
  UQRSHRN_ASISDSHF_N,
  UQSHL_ASIMDSAME_ONLY,
  UQSHL_ASIMDSHF_R,
  UQSHL_ASISDSAME_ONLY,
  UQSHL_ASISDSHF_R,
  UQSHRN_ASIMDSHF_N,
  UQSHRN_ASISDSHF_N,
  UQSUB_ASIMDSAME_ONLY,
  UQSUB_ASISDSAME_ONLY,
  UQXTN_ASIMDMISC_N,
  UQXTN_ASISDMISC_N,
  URECPE_ASIMDMISC_R,
  URHADD_ASIMDSAME_ONLY,
  URSHL_ASIMDSAME_ONLY,
  URSHL_ASISDSAME_ONLY,
  URSHR_ASIMDSHF_R,
  URSHR_ASISDSHF_R,
  URSQRTE_ASIMDMISC_R,
  URSRA_ASIMDSHF_R,
  URSRA_ASISDSHF_R,
  USHLL_ASIMDSHF_L,
  USHL_ASIMDSAME_ONLY,
  USHL_ASISDSAME_ONLY,
  USHR_ASIMDSHF_R,
  USHR_ASISDSHF_R,
  USQADD_ASIMDMISC_R,
  USQADD_ASISDMISC_R,
  USRA_ASIMDSHF_R,
  USRA_ASISDSHF_R,
  USUBL_ASIMDDIFF_L,
  USUBW_ASIMDDIFF_W,
  UXTB_UBFM_32M_BITFIELD,
  UXTH_UBFM_32M_BITFIELD,
  UXTL_USHLL_ASIMDSHF_L,
  UZP1_ASIMDPERM_ONLY,
  UZP2_ASIMDPERM_ONLY,
  WFE_HI_SYSTEM,
  WFI_HI_SYSTEM,
  XTN_ASIMDMISC_N,
  YIELD_HI_SYSTEM,
  ZIP1_ASIMDPERM_ONLY,
  ZIP2_ASIMDPERM_ONLY,
};

union InstImm {
  uint64_t uimm;

#define IMM_GETTER(N) \
  union { \
    int64_t simm##N : N; \
    uint64_t _##N : (64 - N); \
  } __attribute__((packed));

  IMM_GETTER(1)
  IMM_GETTER(2)
  IMM_GETTER(3)
  IMM_GETTER(4)
  IMM_GETTER(5)
  IMM_GETTER(6)
  IMM_GETTER(7)
  IMM_GETTER(8)
  IMM_GETTER(9)

  IMM_GETTER(10)
  IMM_GETTER(11)
  IMM_GETTER(12)
  IMM_GETTER(13)
  IMM_GETTER(14)
  IMM_GETTER(15)
  IMM_GETTER(16)
  IMM_GETTER(17)
  IMM_GETTER(18)
  IMM_GETTER(19)

  IMM_GETTER(20)
  IMM_GETTER(21)
  IMM_GETTER(22)
  IMM_GETTER(23)
  IMM_GETTER(24)
  IMM_GETTER(25)
  IMM_GETTER(26)
  IMM_GETTER(27)
  IMM_GETTER(28)
  IMM_GETTER(29)

  IMM_GETTER(30)
  IMM_GETTER(31)

#undef IMM_GETTER

} __attribute__((packed));
static_assert(sizeof(InstImm) == 8, "");

#ifdef REMILL_AARCH_STRICT_REGNUM
enum class RegNum : uint8_t;
#else
using RegNum = uint8_t;
#endif

struct InstData {
  InstForm iform;
  InstName iclass;
  InstImm immhi_immlo;
  InstImm imm26;  // B_only_branch_imm, ...
  InstImm imm19;  // B_only_condbranch, ...
  InstImm immhi;  // ADRP_only_pcreladdr, ...
  InstImm imm16;  // MOVK_64_movewide, ...
  InstImm imm14;  // TBZ_only_testbranch, ...
  InstImm imm12;  // LDRSW_64_ldst_pos, ...
  InstImm imm9;  // PRFUM_P_ldst_unscaled, ...
  InstImm imm8;  // FMOV_D_floatimm, ...
  InstImm imm7;  // STP_64_ldstpair_off, ...
  InstImm imm6;  // ORN_64_log_shift, ...
  InstImm immr;  // SXTH_SBFM_64M_bitfield, ...
  InstImm imms;  // SXTH_SBFM_64M_bitfield, ...
  InstImm imm5;  // UMOV_asimdins_X_x, ...
  InstImm imm4;  // EXT_asimdext_only, ...
  InstImm immh;  // SQSHRUN_asimdshf_N, ...
  InstImm imm3;  // SUB_64_addsub_ext, ...
  InstImm immb;  // SQSHRUN_asimdshf_N, ...
  InstImm immlo;  // ADRP_only_pcreladdr, ...
  uint8_t op3;  // RET_64R_branch_reg, ...
  uint8_t opcode;  // LD3_asisdlsop_DX3_r3d, ...
  uint8_t opcode2;  // UDIV_64_dp_2src, ...
  uint8_t scale;  // UCVTF_D64_float2fix, ...
  RegNum Ra;  // FNMADD_D_floatdp3, ...
  RegNum Rd;  // ORN_64_log_shift, ...
  RegNum Rm;  // ORN_64_log_shift, ...
  RegNum Rn;  // LDCLRLB_32_memop, ...
  RegNum Rs;  // LDCLRLB_32_memop, ...
  RegNum Rt;  // LDCLRLB_32_memop, ...
  RegNum Rt2;  // STP_64_ldstpair_off, ...
  uint8_t b40;  // TBZ_only_testbranch, ...
  uint8_t op2;  // EXT_asimdext_only, ...
  uint8_t op4;  // RET_64R_branch_reg, ...
  uint8_t CRm;  // SYS_CR_system, ...
  uint8_t CRn;  // SYS_CR_system, ...
  uint8_t cmode;  // FMOV_asimdimm_D2_d, ...
  uint8_t cond;  // FCCMP_D_floatccmp, ...
  uint8_t nzcv;  // FCCMP_D_floatccmp, ...
  uint8_t opc;  // LDCLRLB_32_memop, ...
  uint8_t Op3;  // FMINNM_asimdsamefp16_only, ...
  uint8_t op1;  // SYS_CR_system, ...
  uint8_t op31;  // MUL_MADD_64A_dp_3src, ...
  uint8_t option;  // STR_Q_ldst_regoff, ...
  uint8_t rmode;  // FCVTNU_64D_float2int, ...
  uint8_t LL;  // SVC_EX_exception, ...
  uint8_t hw;  // MOVK_64_movewide, ...
  uint8_t len;  // TBL_asimdtbl_L1_1, ...
  uint8_t op;  // SUB_64_addsub_ext, ...
  uint8_t op0;  // SYS_CR_system, ...
  uint8_t op21;  // ROR_EXTR_64_extract, ...
  uint8_t op54;  // SMADDL_64WA_dp_3src, ...
  uint8_t opc2;  // BSL_asimdsame_only, ...
  uint8_t opt;  // SUB_64_addsub_ext, ...
  uint8_t shift;  // ORN_64_log_shift, ...
  uint8_t size;  // LDCLRLB_32_memop, ...
  uint8_t sz;  // FRINTN_asimdmisc_R, ...
  uint8_t type;  // FCCMP_D_floatccmp, ...
  uint8_t A;  // LDCLRLB_32_memop, ...
  uint8_t C;  // CRC32X_64C_dp_2src, ...
  uint8_t D;  // AESMC_B_cryptoaes, ...
  uint8_t E;  // FACGT_asimdsame_only, ...
  uint8_t H;  // MUL_asimdelem_R, ...
  uint8_t L;  // STP_64_ldstpair_off, ...
  uint8_t M;  // FCCMP_D_floatccmp, ...
  uint8_t N;  // ORN_64_log_shift, ...
  uint8_t P;  // SHA256H_QQV_cryptosha3, ...
  uint8_t Q;  // FRINTN_asimdmisc_R, ...
  uint8_t R;  // LDCLRLB_32_memop, ...
  uint8_t S;  // STR_Q_ldst_regoff, ...
  uint8_t U;  // FRINTN_asimdmisc_R, ...
  uint8_t V;  // LDCLRLB_32_memop, ...
  uint8_t a;  // FABD_asimdsamefp16_only, ...
  uint8_t ac;  // FACGT_asimdsame_only, ...
  uint8_t b;  // FMOV_asimdimm_D2_d, ...
  uint8_t b5;  // TBZ_only_testbranch, ...
  uint8_t c;  // FMOV_asimdimm_D2_d, ...
  uint8_t d;  // FMOV_asimdimm_D2_d, ...
  uint8_t e;  // FMOV_asimdimm_D2_d, ...
  uint8_t eq;  // CMGE_asimdsame_only, ...
  uint8_t f;  // FMOV_asimdimm_D2_d, ...
  uint8_t g;  // FMOV_asimdimm_D2_d, ...
  uint8_t h;  // FMOV_asimdimm_D2_d, ...
  uint8_t o0;  // FNMADD_D_floatdp3, ...
  uint8_t o1;  // FRINTN_asimdmisc_R, ...
  uint8_t o2;  // FRINTN_asimdmisc_R, ...
  uint8_t o3;  // LDCLRLB_32_memop, ...
  uint8_t sf;  // ORN_64_log_shift, ...
};

// FRECPX  <Hd>, <Hn>
bool TryDecodeFRECPX_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FRECPX  <V><d>, <V><n>
bool TryDecodeFRECPX_ASISDMISC_R(const InstData &data, Instruction &inst);

// LDP  <Wt1>, <Wt2>, [<Xn|SP>], #<imm>
bool TryDecodeLDP_32_LDSTPAIR_POST(const InstData &data, Instruction &inst);

// LDP  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
bool TryDecodeLDP_64_LDSTPAIR_POST(const InstData &data, Instruction &inst);

// LDP  <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!
bool TryDecodeLDP_32_LDSTPAIR_PRE(const InstData &data, Instruction &inst);

// LDP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
bool TryDecodeLDP_64_LDSTPAIR_PRE(const InstData &data, Instruction &inst);

// LDP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeLDP_32_LDSTPAIR_OFF(const InstData &data, Instruction &inst);

// LDP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeLDP_64_LDSTPAIR_OFF(const InstData &data, Instruction &inst);

// STSMAXH  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMAXH_32S_MEMOP(const InstData &data, Instruction &inst);

// STSMAXLH  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMAXLH_32S_MEMOP(const InstData &data, Instruction &inst);

// REV  <Wd>, <Wn>
bool TryDecodeREV_32_DP_1SRC(const InstData &data, Instruction &inst);

// REV  <Xd>, <Xn>
bool TryDecodeREV_64_DP_1SRC(const InstData &data, Instruction &inst);

// UBFX  <Wd>, <Wn>, #<lsb>, #<width>
bool TryDecodeUBFX_UBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// UBFX  <Xd>, <Xn>, #<lsb>, #<width>
bool TryDecodeUBFX_UBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// UMINV  <V><d>, <Vn>.<T>
bool TryDecodeUMINV_ASIMDALL_ONLY(const InstData &data, Instruction &inst);

// FADDP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFADDP_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FADDP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFADDP_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FABS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFABS_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FABS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFABS_ASIMDMISC_R(const InstData &data, Instruction &inst);

// MADD  <Wd>, <Wn>, <Wm>, <Wa>
bool TryDecodeMADD_32A_DP_3SRC(const InstData &data, Instruction &inst);

// MADD  <Xd>, <Xn>, <Xm>, <Xa>
bool TryDecodeMADD_64A_DP_3SRC(const InstData &data, Instruction &inst);

// SCVTF  <V><d>, <V><n>, #<fbits>
bool TryDecodeSCVTF_ASISDSHF_C(const InstData &data, Instruction &inst);

// SCVTF  <Vd>.<T>, <Vn>.<T>, #<fbits>
bool TryDecodeSCVTF_ASIMDSHF_C(const InstData &data, Instruction &inst);

// CLZ  <Vd>.<T>, <Vn>.<T>
bool TryDecodeCLZ_ASIMDMISC_R(const InstData &data, Instruction &inst);

// FCVT  <Sd>, <Hn>
bool TryDecodeFCVT_SH_FLOATDP1(const InstData &data, Instruction &inst);

// FCVT  <Dd>, <Hn>
bool TryDecodeFCVT_DH_FLOATDP1(const InstData &data, Instruction &inst);

// FCVT  <Hd>, <Sn>
bool TryDecodeFCVT_HS_FLOATDP1(const InstData &data, Instruction &inst);

// FCVT  <Dd>, <Sn>
bool TryDecodeFCVT_DS_FLOATDP1(const InstData &data, Instruction &inst);

// FCVT  <Hd>, <Dn>
bool TryDecodeFCVT_HD_FLOATDP1(const InstData &data, Instruction &inst);

// FCVT  <Sd>, <Dn>
bool TryDecodeFCVT_SD_FLOATDP1(const InstData &data, Instruction &inst);

// LDLARH  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDLARH_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// LDUR  <Bt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDUR_B_LDST_UNSCALED(const InstData &data, Instruction &inst);

// LDUR  <Ht>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDUR_H_LDST_UNSCALED(const InstData &data, Instruction &inst);

// LDUR  <St>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDUR_S_LDST_UNSCALED(const InstData &data, Instruction &inst);

// LDUR  <Dt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDUR_D_LDST_UNSCALED(const InstData &data, Instruction &inst);

// LDUR  <Qt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDUR_Q_LDST_UNSCALED(const InstData &data, Instruction &inst);

// CLZ  <Wd>, <Wn>
bool TryDecodeCLZ_32_DP_1SRC(const InstData &data, Instruction &inst);

// CLZ  <Xd>, <Xn>
bool TryDecodeCLZ_64_DP_1SRC(const InstData &data, Instruction &inst);

// LSR  <Wd>, <Wn>, <Wm>
bool TryDecodeLSR_LSRV_32_DP_2SRC(const InstData &data, Instruction &inst);

// LSR  <Xd>, <Xn>, <Xm>
bool TryDecodeLSR_LSRV_64_DP_2SRC(const InstData &data, Instruction &inst);

// FCVTN{2}  <Vd>.<Tb>, <Vn>.<Ta>
bool TryDecodeFCVTN_ASIMDMISC_N(const InstData &data, Instruction &inst);

// CNEG  <Wd>, <Wn>, <cond>
bool TryDecodeCNEG_CSNEG_32_CONDSEL(const InstData &data, Instruction &inst);

// CNEG  <Xd>, <Xn>, <cond>
bool TryDecodeCNEG_CSNEG_64_CONDSEL(const InstData &data, Instruction &inst);

// LDRSH  <Wt>, [<Xn|SP>], #<simm>
bool TryDecodeLDRSH_32_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDRSH  <Xt>, [<Xn|SP>], #<simm>
bool TryDecodeLDRSH_64_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDRSH  <Wt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDRSH_32_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDRSH  <Xt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDRSH_64_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDRSH  <Wt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDRSH_32_LDST_POS(const InstData &data, Instruction &inst);

// LDRSH  <Xt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDRSH_64_LDST_POS(const InstData &data, Instruction &inst);

// ABS  <V><d>, <V><n>
bool TryDecodeABS_ASISDMISC_R(const InstData &data, Instruction &inst);

// ABS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeABS_ASIMDMISC_R(const InstData &data, Instruction &inst);

// CMP  <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
bool TryDecodeCMP_SUBS_32S_ADDSUB_EXT(const InstData &data, Instruction &inst);

// CMP  <Xn|SP>, <R><m>{, <extend> {#<amount>}}
bool TryDecodeCMP_SUBS_64S_ADDSUB_EXT(const InstData &data, Instruction &inst);

// HINT  #<imm>
bool TryDecodeHINT_1(const InstData &data, Instruction &inst);

// HINT  #<imm>
bool TryDecodeHINT_2(const InstData &data, Instruction &inst);

// HINT  #<imm>
bool TryDecodeHINT_3(const InstData &data, Instruction &inst);

// FMAX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMAX_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FMAX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMAX_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FMIN  <Hd>, <Hn>, <Hm>
bool TryDecodeFMIN_H_FLOATDP2(const InstData &data, Instruction &inst);

// FMIN  <Sd>, <Sn>, <Sm>
bool TryDecodeFMIN_S_FLOATDP2(const InstData &data, Instruction &inst);

// FMIN  <Dd>, <Dn>, <Dm>
bool TryDecodeFMIN_D_FLOATDP2(const InstData &data, Instruction &inst);

// UMLSL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
bool TryDecodeUMLSL_ASIMDELEM_L(const InstData &data, Instruction &inst);

// FMAXNM  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMAXNM_ASIMDSAMEFP16_ONLY(const InstData &data,
                                        Instruction &inst);

// FMAXNM  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMAXNM_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FCVTPS  <Wd>, <Hn>
bool TryDecodeFCVTPS_32H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTPS  <Xd>, <Hn>
bool TryDecodeFCVTPS_64H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTPS  <Wd>, <Sn>
bool TryDecodeFCVTPS_32S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTPS  <Xd>, <Sn>
bool TryDecodeFCVTPS_64S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTPS  <Wd>, <Dn>
bool TryDecodeFCVTPS_32D_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTPS  <Xd>, <Dn>
bool TryDecodeFCVTPS_64D_FLOAT2INT(const InstData &data, Instruction &inst);

// FMINNM  <Hd>, <Hn>, <Hm>
bool TryDecodeFMINNM_H_FLOATDP2(const InstData &data, Instruction &inst);

// FMINNM  <Sd>, <Sn>, <Sm>
bool TryDecodeFMINNM_S_FLOATDP2(const InstData &data, Instruction &inst);

// FMINNM  <Dd>, <Dn>, <Dm>
bool TryDecodeFMINNM_D_FLOATDP2(const InstData &data, Instruction &inst);

// LDTRSW  <Xt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDTRSW_64_LDST_UNPRIV(const InstData &data, Instruction &inst);

// FSQRT  <Hd>, <Hn>
bool TryDecodeFSQRT_H_FLOATDP1(const InstData &data, Instruction &inst);

// FSQRT  <Sd>, <Sn>
bool TryDecodeFSQRT_S_FLOATDP1(const InstData &data, Instruction &inst);

// FSQRT  <Dd>, <Dn>
bool TryDecodeFSQRT_D_FLOATDP1(const InstData &data, Instruction &inst);

// LDEORA  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEORA_32_MEMOP(const InstData &data, Instruction &inst);

// LDEORAL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEORAL_32_MEMOP(const InstData &data, Instruction &inst);

// LDEOR  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEOR_32_MEMOP(const InstData &data, Instruction &inst);

// LDEORL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEORL_32_MEMOP(const InstData &data, Instruction &inst);

// LDEORA  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDEORA_64_MEMOP(const InstData &data, Instruction &inst);

// LDEORAL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDEORAL_64_MEMOP(const InstData &data, Instruction &inst);

// LDEOR  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDEOR_64_MEMOP(const InstData &data, Instruction &inst);

// LDEORL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDEORL_64_MEMOP(const InstData &data, Instruction &inst);

// SHRN{2}  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
bool TryDecodeSHRN_ASIMDSHF_N(const InstData &data, Instruction &inst);

// FRINTM  <Hd>, <Hn>
bool TryDecodeFRINTM_H_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTM  <Sd>, <Sn>
bool TryDecodeFRINTM_S_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTM  <Dd>, <Dn>
bool TryDecodeFRINTM_D_FLOATDP1(const InstData &data, Instruction &inst);

// LDUMINAB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMINAB_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMINALB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMINALB_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMINB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMINB_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMINLB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMINLB_32_MEMOP(const InstData &data, Instruction &inst);

// SHA256SU0  <Vd>.4S, <Vn>.4S
bool TryDecodeSHA256SU0_VV_CRYPTOSHA2(const InstData &data, Instruction &inst);

// FMINP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMINP_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FMINP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMINP_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// BFM  <Wd>, <Wn>, #<immr>, #<imms>
bool TryDecodeBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// BFM  <Xd>, <Xn>, #<immr>, #<imms>
bool TryDecodeBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// LDR  <Bt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
bool TryDecodeLDR_B_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDR  <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
bool TryDecodeLDR_BL_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDR  <Ht>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeLDR_H_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDR  <St>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeLDR_S_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDR  <Dt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeLDR_D_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDR  <Qt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeLDR_Q_LDST_REGOFF(const InstData &data, Instruction &inst);

// SQRDMLSH  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
bool TryDecodeSQRDMLSH_ASISDELEM_R(const InstData &data, Instruction &inst);

// SQRDMLSH  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
bool TryDecodeSQRDMLSH_ASIMDELEM_R(const InstData &data, Instruction &inst);

// ANDS  <Wd>, <Wn>, #<imm>
bool TryDecodeANDS_32S_LOG_IMM(const InstData &data, Instruction &inst);

// ANDS  <Xd>, <Xn>, #<imm>
bool TryDecodeANDS_64S_LOG_IMM(const InstData &data, Instruction &inst);

// LDCLRA  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLRA_32_MEMOP(const InstData &data, Instruction &inst);

// LDCLRAL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLRAL_32_MEMOP(const InstData &data, Instruction &inst);

// LDCLR  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLR_32_MEMOP(const InstData &data, Instruction &inst);

// LDCLRL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLRL_32_MEMOP(const InstData &data, Instruction &inst);

// LDCLRA  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDCLRA_64_MEMOP(const InstData &data, Instruction &inst);

// LDCLRAL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDCLRAL_64_MEMOP(const InstData &data, Instruction &inst);

// LDCLR  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDCLR_64_MEMOP(const InstData &data, Instruction &inst);

// LDCLRL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDCLRL_64_MEMOP(const InstData &data, Instruction &inst);

// UABD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUABD_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// STURB  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTURB_32_LDST_UNSCALED(const InstData &data, Instruction &inst);

// ORR  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeORR_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FRINTA  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTA_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FRINTA  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTA_ASIMDMISC_R(const InstData &data, Instruction &inst);

// SUBS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeSUBS_32_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// SUBS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeSUBS_64_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// STXP  <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
bool TryDecodeSTXP_SP32_LDSTEXCL(const InstData &data, Instruction &inst);

// STXP  <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
bool TryDecodeSTXP_SP64_LDSTEXCL(const InstData &data, Instruction &inst);

// SBFX  <Wd>, <Wn>, #<lsb>, #<width>
bool TryDecodeSBFX_SBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// SBFX  <Xd>, <Xn>, #<lsb>, #<width>
bool TryDecodeSBFX_SBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// LDXP  <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
bool TryDecodeLDXP_LP32_LDSTEXCL(const InstData &data, Instruction &inst);

// LDXP  <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
bool TryDecodeLDXP_LP64_LDSTEXCL(const InstData &data, Instruction &inst);

// ORR  <Wd|WSP>, <Wn>, #<imm>
bool TryDecodeORR_32_LOG_IMM(const InstData &data, Instruction &inst);

// ORR  <Xd|SP>, <Xn>, #<imm>
bool TryDecodeORR_64_LOG_IMM(const InstData &data, Instruction &inst);

// UCVTF  <Hd>, <Hn>
bool TryDecodeUCVTF_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// UCVTF  <V><d>, <V><n>
bool TryDecodeUCVTF_ASISDMISC_R(const InstData &data, Instruction &inst);

// UCVTF  <Vd>.<T>, <Vn>.<T>
bool TryDecodeUCVTF_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// UCVTF  <Vd>.<T>, <Vn>.<T>
bool TryDecodeUCVTF_ASIMDMISC_R(const InstData &data, Instruction &inst);

// SQDMULH  <V><d>, <V><n>, <V><m>
bool TryDecodeSQDMULH_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// SQDMULH  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSQDMULH_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FCVTL{2}  <Vd>.<Ta>, <Vn>.<Tb>
bool TryDecodeFCVTL_ASIMDMISC_L(const InstData &data, Instruction &inst);

// CCMN  <Wn>, #<imm>, #<nzcv>, <cond>
bool TryDecodeCCMN_32_CONDCMP_IMM(const InstData &data, Instruction &inst);

// CCMN  <Xn>, #<imm>, #<nzcv>, <cond>
bool TryDecodeCCMN_64_CONDCMP_IMM(const InstData &data, Instruction &inst);

// DMB  <option>|#<imm>
bool TryDecodeDMB_BO_SYSTEM(const InstData &data, Instruction &inst);

// YIELD
bool TryDecodeYIELD_HI_SYSTEM(const InstData &data, Instruction &inst);

// UXTH  <Wd>, <Wn>
bool TryDecodeUXTH_UBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// STADD  <Ws>, [<Xn|SP>]
bool TryDecodeSTADD_32S_MEMOP(const InstData &data, Instruction &inst);

// STADDL  <Ws>, [<Xn|SP>]
bool TryDecodeSTADDL_32S_MEMOP(const InstData &data, Instruction &inst);

// STADD  <Xs>, [<Xn|SP>]
bool TryDecodeSTADD_64S_MEMOP(const InstData &data, Instruction &inst);

// STADDL  <Xs>, [<Xn|SP>]
bool TryDecodeSTADDL_64S_MEMOP(const InstData &data, Instruction &inst);

// USRA  <V><d>, <V><n>, #<shift>
bool TryDecodeUSRA_ASISDSHF_R(const InstData &data, Instruction &inst);

// USRA  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeUSRA_ASIMDSHF_R(const InstData &data, Instruction &inst);

// MOV  <Wd>, #<imm>
bool TryDecodeMOV_MOVZ_32_MOVEWIDE(const InstData &data, Instruction &inst);

// MOV  <Xd>, #<imm>
bool TryDecodeMOV_MOVZ_64_MOVEWIDE(const InstData &data, Instruction &inst);

// MLS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeMLS_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T> }, [<Xn|SP>]
bool TryDecodeST1_ASISDLSE_R1_1V(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]
bool TryDecodeST1_ASISDLSE_R2_2V(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]
bool TryDecodeST1_ASISDLSE_R3_3V(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]
bool TryDecodeST1_ASISDLSE_R4_4V(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeST1_ASISDLSEP_I1_I1(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeST1_ASISDLSEP_R1_R1(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeST1_ASISDLSEP_I2_I2(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeST1_ASISDLSEP_R2_R2(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeST1_ASISDLSEP_I3_I3(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeST1_ASISDLSEP_R3_R3(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeST1_ASISDLSEP_I4_I4(const InstData &data, Instruction &inst);

// ST1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeST1_ASISDLSEP_R4_R4(const InstData &data, Instruction &inst);

// AESIMC  <Vd>.16B, <Vn>.16B
bool TryDecodeAESIMC_B_CRYPTOAES(const InstData &data, Instruction &inst);

// UMULH  <Xd>, <Xn>, <Xm>
bool TryDecodeUMULH_64_DP_3SRC(const InstData &data, Instruction &inst);

// UADDW{2}  <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>
bool TryDecodeUADDW_ASIMDDIFF_W(const InstData &data, Instruction &inst);

// STRH  <Wt>, [<Xn|SP>], #<simm>
bool TryDecodeSTRH_32_LDST_IMMPOST(const InstData &data, Instruction &inst);

// STRH  <Wt>, [<Xn|SP>, #<simm>]!
bool TryDecodeSTRH_32_LDST_IMMPRE(const InstData &data, Instruction &inst);

// STRH  <Wt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeSTRH_32_LDST_POS(const InstData &data, Instruction &inst);

// SCVTF  <Hd>, <Wn>
bool TryDecodeSCVTF_H32_FLOAT2INT(const InstData &data, Instruction &inst);

// SCVTF  <Sd>, <Wn>
bool TryDecodeSCVTF_S32_FLOAT2INT(const InstData &data, Instruction &inst);

// SCVTF  <Dd>, <Wn>
bool TryDecodeSCVTF_D32_FLOAT2INT(const InstData &data, Instruction &inst);

// SCVTF  <Hd>, <Xn>
bool TryDecodeSCVTF_H64_FLOAT2INT(const InstData &data, Instruction &inst);

// SCVTF  <Sd>, <Xn>
bool TryDecodeSCVTF_S64_FLOAT2INT(const InstData &data, Instruction &inst);

// SCVTF  <Dd>, <Xn>
bool TryDecodeSCVTF_D64_FLOAT2INT(const InstData &data, Instruction &inst);

// STUMAXB  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMAXB_32S_MEMOP(const InstData &data, Instruction &inst);

// STUMAXLB  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMAXLB_32S_MEMOP(const InstData &data, Instruction &inst);

// CMHI  <V><d>, <V><n>, <V><m>
bool TryDecodeCMHI_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// CMHI  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeCMHI_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SQDMLAL  <Va><d>, <Vb><n>, <Vb><m>
bool TryDecodeSQDMLAL_ASISDDIFF_ONLY(const InstData &data, Instruction &inst);

// SQDMLAL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeSQDMLAL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// CBNZ  <Wt>, <label>
bool TryDecodeCBNZ_32_COMPBRANCH(const InstData &data, Instruction &inst);

// CBNZ  <Xt>, <label>
bool TryDecodeCBNZ_64_COMPBRANCH(const InstData &data, Instruction &inst);

// SEVL
bool TryDecodeSEVL_HI_SYSTEM(const InstData &data, Instruction &inst);

// FRINTX  <Hd>, <Hn>
bool TryDecodeFRINTX_H_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTX  <Sd>, <Sn>
bool TryDecodeFRINTX_S_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTX  <Dd>, <Dn>
bool TryDecodeFRINTX_D_FLOATDP1(const InstData &data, Instruction &inst);

// CMN  <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeCMN_ADDS_32_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// CMN  <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeCMN_ADDS_64_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// SMIN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSMIN_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// LDUMAXAB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAXAB_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMAXALB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAXALB_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMAXB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAXB_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMAXLB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAXLB_32_MEMOP(const InstData &data, Instruction &inst);

// AESE  <Vd>.16B, <Vn>.16B
bool TryDecodeAESE_B_CRYPTOAES(const InstData &data, Instruction &inst);

// SMAXP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSMAXP_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// STXR  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTXR_SR32_LDSTEXCL(const InstData &data, Instruction &inst);

// STXR  <Ws>, <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeSTXR_SR64_LDSTEXCL(const InstData &data, Instruction &inst);

// SUB  <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
bool TryDecodeSUB_32_ADDSUB_IMM(const InstData &data, Instruction &inst);

// SUB  <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
bool TryDecodeSUB_64_ADDSUB_IMM(const InstData &data, Instruction &inst);

// CMLT  <V><d>, <V><n>, #0
bool TryDecodeCMLT_ASISDMISC_Z(const InstData &data, Instruction &inst);

// CMLT  <Vd>.<T>, <Vn>.<T>, #0
bool TryDecodeCMLT_ASIMDMISC_Z(const InstData &data, Instruction &inst);

// FCMEQ  <Hd>, <Hn>, <Hm>
bool TryDecodeFCMEQ_ASISDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FCMEQ  <V><d>, <V><n>, <V><m>
bool TryDecodeFCMEQ_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// FCMEQ  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFCMEQ_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FCMEQ  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFCMEQ_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// CLREX  {#<imm>}
bool TryDecodeCLREX_BN_SYSTEM(const InstData &data, Instruction &inst);

// FSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFSUB_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFSUB_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SHLL{2}  <Vd>.<Ta>, <Vn>.<Tb>, #<shift>
bool TryDecodeSHLL_ASIMDMISC_S(const InstData &data, Instruction &inst);

// SQADD  <V><d>, <V><n>, <V><m>
bool TryDecodeSQADD_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// SQADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSQADD_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// BIC  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeBIC_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SUB  <V><d>, <V><n>, <V><m>
bool TryDecodeSUB_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// SUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSUB_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SWPA  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWPA_32_MEMOP(const InstData &data, Instruction &inst);

// SWPAL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWPAL_32_MEMOP(const InstData &data, Instruction &inst);

// SWP  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWP_32_MEMOP(const InstData &data, Instruction &inst);

// SWPL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWPL_32_MEMOP(const InstData &data, Instruction &inst);

// SWPA  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeSWPA_64_MEMOP(const InstData &data, Instruction &inst);

// SWPAL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeSWPAL_64_MEMOP(const InstData &data, Instruction &inst);

// SWP  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeSWP_64_MEMOP(const InstData &data, Instruction &inst);

// SWPL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeSWPL_64_MEMOP(const InstData &data, Instruction &inst);

// SMC  #<imm>
bool TryDecodeSMC_EX_EXCEPTION(const InstData &data, Instruction &inst);

// LDUR  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDUR_32_LDST_UNSCALED(const InstData &data, Instruction &inst);

// LDUR  <Xt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDUR_64_LDST_UNSCALED(const InstData &data, Instruction &inst);

// CMGE  <V><d>, <V><n>, #0
bool TryDecodeCMGE_ASISDMISC_Z(const InstData &data, Instruction &inst);

// CMGE  <Vd>.<T>, <Vn>.<T>, #0
bool TryDecodeCMGE_ASIMDMISC_Z(const InstData &data, Instruction &inst);

// UCVTF  <V><d>, <V><n>, #<fbits>
bool TryDecodeUCVTF_ASISDSHF_C(const InstData &data, Instruction &inst);

// UCVTF  <Vd>.<T>, <Vn>.<T>, #<fbits>
bool TryDecodeUCVTF_ASIMDSHF_C(const InstData &data, Instruction &inst);

// STLLR  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLLR_SL32_LDSTEXCL(const InstData &data, Instruction &inst);

// STLLR  <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLLR_SL64_LDSTEXCL(const InstData &data, Instruction &inst);

// SSUBL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeSSUBL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// SMLSL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeSMLSL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// MOV  <Wd|WSP>, <Wn|WSP>
bool TryDecodeMOV_ADD_32_ADDSUB_IMM(const InstData &data, Instruction &inst);

// MOV  <Xd|SP>, <Xn|SP>
bool TryDecodeMOV_ADD_64_ADDSUB_IMM(const InstData &data, Instruction &inst);

// STTRB  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTTRB_32_LDST_UNPRIV(const InstData &data, Instruction &inst);

// BIC  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeBIC_32_LOG_SHIFT(const InstData &data, Instruction &inst);

// BIC  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeBIC_64_LOG_SHIFT(const InstData &data, Instruction &inst);

// TST  <Wn>, #<imm>
bool TryDecodeTST_ANDS_32S_LOG_IMM(const InstData &data, Instruction &inst);

// TST  <Xn>, #<imm>
bool TryDecodeTST_ANDS_64S_LOG_IMM(const InstData &data, Instruction &inst);

// AND  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeAND_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// STLXP  <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
bool TryDecodeSTLXP_SP32_LDSTEXCL(const InstData &data, Instruction &inst);

// STLXP  <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
bool TryDecodeSTLXP_SP64_LDSTEXCL(const InstData &data, Instruction &inst);

// SQRSHL  <V><d>, <V><n>, <V><m>
bool TryDecodeSQRSHL_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// SQRSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSQRSHL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// UABAL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeUABAL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// MVNI  <Vd>.<T>, #<imm8>{, LSL #<amount>}
bool TryDecodeMVNI_ASIMDIMM_L_HL(const InstData &data, Instruction &inst);

// MVNI  <Vd>.<T>, #<imm8>{, LSL #<amount>}
bool TryDecodeMVNI_ASIMDIMM_L_SL(const InstData &data, Instruction &inst);

// MVNI  <Vd>.<T>, #<imm8>, MSL #<amount>
bool TryDecodeMVNI_ASIMDIMM_M_SM(const InstData &data, Instruction &inst);

// MOV  <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]
bool TryDecodeMOV_INS_ASIMDINS_IV_V(const InstData &data, Instruction &inst);

// SRSHR  <V><d>, <V><n>, #<shift>
bool TryDecodeSRSHR_ASISDSHF_R(const InstData &data, Instruction &inst);

// SRSHR  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeSRSHR_ASIMDSHF_R(const InstData &data, Instruction &inst);

// LSL  <Wd>, <Wn>, #<shift>
bool TryDecodeLSL_UBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// LSL  <Xd>, <Xn>, #<shift>
bool TryDecodeLSL_UBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// CLS  <Wd>, <Wn>
bool TryDecodeCLS_32_DP_1SRC(const InstData &data, Instruction &inst);

// CLS  <Xd>, <Xn>
bool TryDecodeCLS_64_DP_1SRC(const InstData &data, Instruction &inst);

// SEV
bool TryDecodeSEV_HI_SYSTEM(const InstData &data, Instruction &inst);

// UMIN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUMIN_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FMULX  <Hd>, <Hn>, <Hm>
bool TryDecodeFMULX_ASISDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FMULX  <V><d>, <V><n>, <V><m>
bool TryDecodeFMULX_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// FMULX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMULX_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FMULX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMULX_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// ADDS  <Wd>, <Wn|WSP>, #<imm>{, <shift>}
bool TryDecodeADDS_32S_ADDSUB_IMM(const InstData &data, Instruction &inst);

// ADDS  <Xd>, <Xn|SP>, #<imm>{, <shift>}
bool TryDecodeADDS_64S_ADDSUB_IMM(const InstData &data, Instruction &inst);

// UQSHL  <V><d>, <V><n>, <V><m>
bool TryDecodeUQSHL_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// UQSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUQSHL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// STEORB  <Ws>, [<Xn|SP>]
bool TryDecodeSTEORB_32S_MEMOP(const InstData &data, Instruction &inst);

// STEORLB  <Ws>, [<Xn|SP>]
bool TryDecodeSTEORLB_32S_MEMOP(const InstData &data, Instruction &inst);

// LDPSW  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
bool TryDecodeLDPSW_64_LDSTPAIR_POST(const InstData &data, Instruction &inst);

// LDPSW  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
bool TryDecodeLDPSW_64_LDSTPAIR_PRE(const InstData &data, Instruction &inst);

// LDPSW  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeLDPSW_64_LDSTPAIR_OFF(const InstData &data, Instruction &inst);

// STUMAXH  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMAXH_32S_MEMOP(const InstData &data, Instruction &inst);

// STUMAXLH  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMAXLH_32S_MEMOP(const InstData &data, Instruction &inst);

// SMOV  <Wd>, <Vn>.<Ts>[<index>]
bool TryDecodeSMOV_ASIMDINS_W_W(const InstData &data, Instruction &inst);

// SMOV  <Xd>, <Vn>.<Ts>[<index>]
bool TryDecodeSMOV_ASIMDINS_X_X(const InstData &data, Instruction &inst);

// UABA  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUABA_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// STSMINB  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMINB_32S_MEMOP(const InstData &data, Instruction &inst);

// STSMINLB  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMINLB_32S_MEMOP(const InstData &data, Instruction &inst);

// FCMGE  <Hd>, <Hn>, #0.0
bool TryDecodeFCMGE_ASISDMISCFP16_FZ(const InstData &data, Instruction &inst);

// FCMGE  <V><d>, <V><n>, #0.0
bool TryDecodeFCMGE_ASISDMISC_FZ(const InstData &data, Instruction &inst);

// FCMGE  <Vd>.<T>, <Vn>.<T>, #0.0
bool TryDecodeFCMGE_ASIMDMISCFP16_FZ(const InstData &data, Instruction &inst);

// FCMGE  <Vd>.<T>, <Vn>.<T>, #0.0
bool TryDecodeFCMGE_ASIMDMISC_FZ(const InstData &data, Instruction &inst);

// STLLRB  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLLRB_SL32_LDSTEXCL(const InstData &data, Instruction &inst);

// FRINTZ  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTZ_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FRINTZ  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTZ_ASIMDMISC_R(const InstData &data, Instruction &inst);

// STXRH  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTXRH_SR32_LDSTEXCL(const InstData &data, Instruction &inst);

// STEORH  <Ws>, [<Xn|SP>]
bool TryDecodeSTEORH_32S_MEMOP(const InstData &data, Instruction &inst);

// STEORLH  <Ws>, [<Xn|SP>]
bool TryDecodeSTEORLH_32S_MEMOP(const InstData &data, Instruction &inst);

// FMINNMP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMINNMP_ASIMDSAMEFP16_ONLY(const InstData &data,
                                         Instruction &inst);

// FMINNMP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMINNMP_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// LDLAR  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDLAR_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// LDLAR  <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeLDLAR_LR64_LDSTEXCL(const InstData &data, Instruction &inst);

// ADD  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeADD_32_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// ADD  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeADD_64_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// SSHLL{2}  <Vd>.<Ta>, <Vn>.<Tb>, #<shift>
bool TryDecodeSSHLL_ASIMDSHF_L(const InstData &data, Instruction &inst);

// RORV  <Wd>, <Wn>, <Wm>
bool TryDecodeRORV_32_DP_2SRC(const InstData &data, Instruction &inst);

// RORV  <Xd>, <Xn>, <Xm>
bool TryDecodeRORV_64_DP_2SRC(const InstData &data, Instruction &inst);

// STCLRB  <Ws>, [<Xn|SP>]
bool TryDecodeSTCLRB_32S_MEMOP(const InstData &data, Instruction &inst);

// STCLRLB  <Ws>, [<Xn|SP>]
bool TryDecodeSTCLRLB_32S_MEMOP(const InstData &data, Instruction &inst);

// LDARH  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDARH_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// STSMAX  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMAX_32S_MEMOP(const InstData &data, Instruction &inst);

// STSMAXL  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMAXL_32S_MEMOP(const InstData &data, Instruction &inst);

// STSMAX  <Xs>, [<Xn|SP>]
bool TryDecodeSTSMAX_64S_MEMOP(const InstData &data, Instruction &inst);

// STSMAXL  <Xs>, [<Xn|SP>]
bool TryDecodeSTSMAXL_64S_MEMOP(const InstData &data, Instruction &inst);

// BLR  <Xn>
bool TryDecodeBLR_64_BRANCH_REG(const InstData &data, Instruction &inst);

// CMN  <Wn|WSP>, #<imm>{, <shift>}
bool TryDecodeCMN_ADDS_32S_ADDSUB_IMM(const InstData &data, Instruction &inst);

// CMN  <Xn|SP>, #<imm>{, <shift>}
bool TryDecodeCMN_ADDS_64S_ADDSUB_IMM(const InstData &data, Instruction &inst);

// SQDMULL  <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
bool TryDecodeSQDMULL_ASISDELEM_L(const InstData &data, Instruction &inst);

// SQDMULL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
bool TryDecodeSQDMULL_ASIMDELEM_L(const InstData &data, Instruction &inst);

// CSET  <Wd>, <cond>
bool TryDecodeCSET_CSINC_32_CONDSEL(const InstData &data, Instruction &inst);

// CSET  <Xd>, <cond>
bool TryDecodeCSET_CSINC_64_CONDSEL(const InstData &data, Instruction &inst);

// LD1  { <Vt>.B }[<index>], [<Xn|SP>]
bool TryDecodeLD1_ASISDLSO_B1_1B(const InstData &data, Instruction &inst);

// LD1  { <Vt>.H }[<index>], [<Xn|SP>]
bool TryDecodeLD1_ASISDLSO_H1_1H(const InstData &data, Instruction &inst);

// LD1  { <Vt>.S }[<index>], [<Xn|SP>]
bool TryDecodeLD1_ASISDLSO_S1_1S(const InstData &data, Instruction &inst);

// LD1  { <Vt>.D }[<index>], [<Xn|SP>]
bool TryDecodeLD1_ASISDLSO_D1_1D(const InstData &data, Instruction &inst);

// LD1  { <Vt>.B }[<index>], [<Xn|SP>], #1
bool TryDecodeLD1_ASISDLSOP_B1_I1B(const InstData &data, Instruction &inst);

// LD1  { <Vt>.B }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD1_ASISDLSOP_BX1_R1B(const InstData &data, Instruction &inst);

// LD1  { <Vt>.H }[<index>], [<Xn|SP>], #2
bool TryDecodeLD1_ASISDLSOP_H1_I1H(const InstData &data, Instruction &inst);

// LD1  { <Vt>.H }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD1_ASISDLSOP_HX1_R1H(const InstData &data, Instruction &inst);

// LD1  { <Vt>.S }[<index>], [<Xn|SP>], #4
bool TryDecodeLD1_ASISDLSOP_S1_I1S(const InstData &data, Instruction &inst);

// LD1  { <Vt>.S }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD1_ASISDLSOP_SX1_R1S(const InstData &data, Instruction &inst);

// LD1  { <Vt>.D }[<index>], [<Xn|SP>], #8
bool TryDecodeLD1_ASISDLSOP_D1_I1D(const InstData &data, Instruction &inst);

// LD1  { <Vt>.D }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD1_ASISDLSOP_DX1_R1D(const InstData &data, Instruction &inst);

// CCMN  <Wn>, <Wm>, #<nzcv>, <cond>
bool TryDecodeCCMN_32_CONDCMP_REG(const InstData &data, Instruction &inst);

// CCMN  <Xn>, <Xm>, #<nzcv>, <cond>
bool TryDecodeCCMN_64_CONDCMP_REG(const InstData &data, Instruction &inst);

// STNP  <St1>, <St2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeSTNP_S_LDSTNAPAIR_OFFS(const InstData &data, Instruction &inst);

// STNP  <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeSTNP_D_LDSTNAPAIR_OFFS(const InstData &data, Instruction &inst);

// STNP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeSTNP_Q_LDSTNAPAIR_OFFS(const InstData &data, Instruction &inst);

// FSUB  <Hd>, <Hn>, <Hm>
bool TryDecodeFSUB_H_FLOATDP2(const InstData &data, Instruction &inst);

// FSUB  <Sd>, <Sn>, <Sm>
bool TryDecodeFSUB_S_FLOATDP2(const InstData &data, Instruction &inst);

// FSUB  <Dd>, <Dn>, <Dm>
bool TryDecodeFSUB_D_FLOATDP2(const InstData &data, Instruction &inst);

// CSNEG  <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSNEG_32_CONDSEL(const InstData &data, Instruction &inst);

// CSNEG  <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSNEG_64_CONDSEL(const InstData &data, Instruction &inst);

// ASR  <Wd>, <Wn>, <Wm>
bool TryDecodeASR_ASRV_32_DP_2SRC(const InstData &data, Instruction &inst);

// ASR  <Xd>, <Xn>, <Xm>
bool TryDecodeASR_ASRV_64_DP_2SRC(const InstData &data, Instruction &inst);

// UMULL  <Xd>, <Wn>, <Wm>
bool TryDecodeUMULL_UMADDL_64WA_DP_3SRC(const InstData &data,
                                        Instruction &inst);

// FCMGT  <Hd>, <Hn>, <Hm>
bool TryDecodeFCMGT_ASISDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FCMGT  <V><d>, <V><n>, <V><m>
bool TryDecodeFCMGT_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// FCMGT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFCMGT_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FCMGT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFCMGT_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// USUBW{2}  <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>
bool TryDecodeUSUBW_ASIMDDIFF_W(const InstData &data, Instruction &inst);

// REV32  <Xd>, <Xn>
bool TryDecodeREV32_64_DP_1SRC(const InstData &data, Instruction &inst);

// FSQRT  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFSQRT_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FSQRT  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFSQRT_ASIMDMISC_R(const InstData &data, Instruction &inst);

// LSL  <Wd>, <Wn>, <Wm>
bool TryDecodeLSL_LSLV_32_DP_2SRC(const InstData &data, Instruction &inst);

// LSL  <Xd>, <Xn>, <Xm>
bool TryDecodeLSL_LSLV_64_DP_2SRC(const InstData &data, Instruction &inst);

// EXTR  <Wd>, <Wn>, <Wm>, #<lsb>
bool TryDecodeEXTR_32_EXTRACT(const InstData &data, Instruction &inst);

// EXTR  <Xd>, <Xn>, <Xm>, #<lsb>
bool TryDecodeEXTR_64_EXTRACT(const InstData &data, Instruction &inst);

// FCVTAU  <Hd>, <Hn>
bool TryDecodeFCVTAU_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTAU  <V><d>, <V><n>
bool TryDecodeFCVTAU_ASISDMISC_R(const InstData &data, Instruction &inst);

// FCVTAU  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTAU_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTAU  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTAU_ASIMDMISC_R(const InstData &data, Instruction &inst);

// BFXIL  <Wd>, <Wn>, #<lsb>, #<width>
bool TryDecodeBFXIL_BFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// BFXIL  <Xd>, <Xn>, #<lsb>, #<width>
bool TryDecodeBFXIL_BFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// ZIP1  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeZIP1_ASIMDPERM_ONLY(const InstData &data, Instruction &inst);

// LDSETAH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSETAH_32_MEMOP(const InstData &data, Instruction &inst);

// LDSETALH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSETALH_32_MEMOP(const InstData &data, Instruction &inst);

// LDSETH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSETH_32_MEMOP(const InstData &data, Instruction &inst);

// LDSETLH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSETLH_32_MEMOP(const InstData &data, Instruction &inst);

// LDR  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeLDR_32_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDR  <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeLDR_64_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDADDAH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADDAH_32_MEMOP(const InstData &data, Instruction &inst);

// LDADDALH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADDALH_32_MEMOP(const InstData &data, Instruction &inst);

// LDADDH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADDH_32_MEMOP(const InstData &data, Instruction &inst);

// LDADDLH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADDLH_32_MEMOP(const InstData &data, Instruction &inst);

// ANDS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeANDS_32_LOG_SHIFT(const InstData &data, Instruction &inst);

// ANDS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeANDS_64_LOG_SHIFT(const InstData &data, Instruction &inst);

// LD3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]
bool TryDecodeLD3_ASISDLSE_R3(const InstData &data, Instruction &inst);

// LD3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeLD3_ASISDLSEP_I3_I(const InstData &data, Instruction &inst);

// LD3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeLD3_ASISDLSEP_R3_R(const InstData &data, Instruction &inst);

// FMUL  <Hd>, <Hn>, <Hm>
bool TryDecodeFMUL_H_FLOATDP2(const InstData &data, Instruction &inst);

// FMUL  <Sd>, <Sn>, <Sm>
bool TryDecodeFMUL_S_FLOATDP2(const InstData &data, Instruction &inst);

// FMUL  <Dd>, <Dn>, <Dm>
bool TryDecodeFMUL_D_FLOATDP2(const InstData &data, Instruction &inst);

// LDAXR  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDAXR_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// LDAXR  <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeLDAXR_LR64_LDSTEXCL(const InstData &data, Instruction &inst);

// LDRB  <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
bool TryDecodeLDRB_32B_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDRB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
bool TryDecodeLDRB_32BL_LDST_REGOFF(const InstData &data, Instruction &inst);

// UADALP  <Vd>.<Ta>, <Vn>.<Tb>
bool TryDecodeUADALP_ASIMDMISC_P(const InstData &data, Instruction &inst);

// FRINTX  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTX_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FRINTX  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTX_ASIMDMISC_R(const InstData &data, Instruction &inst);

// HLT  #<imm>
bool TryDecodeHLT_EX_EXCEPTION(const InstData &data, Instruction &inst);

// SABA  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSABA_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FMAX  <Hd>, <Hn>, <Hm>
bool TryDecodeFMAX_H_FLOATDP2(const InstData &data, Instruction &inst);

// FMAX  <Sd>, <Sn>, <Sm>
bool TryDecodeFMAX_S_FLOATDP2(const InstData &data, Instruction &inst);

// FMAX  <Dd>, <Dn>, <Dm>
bool TryDecodeFMAX_D_FLOATDP2(const InstData &data, Instruction &inst);

// AESD  <Vd>.16B, <Vn>.16B
bool TryDecodeAESD_B_CRYPTOAES(const InstData &data, Instruction &inst);

// AESMC  <Vd>.16B, <Vn>.16B
bool TryDecodeAESMC_B_CRYPTOAES(const InstData &data, Instruction &inst);

// LD2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>]
bool TryDecodeLD2_ASISDLSO_B2_2B(const InstData &data, Instruction &inst);

// LD2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>]
bool TryDecodeLD2_ASISDLSO_H2_2H(const InstData &data, Instruction &inst);

// LD2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>]
bool TryDecodeLD2_ASISDLSO_S2_2S(const InstData &data, Instruction &inst);

// LD2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>]
bool TryDecodeLD2_ASISDLSO_D2_2D(const InstData &data, Instruction &inst);

// LD2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2
bool TryDecodeLD2_ASISDLSOP_B2_I2B(const InstData &data, Instruction &inst);

// LD2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD2_ASISDLSOP_BX2_R2B(const InstData &data, Instruction &inst);

// LD2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4
bool TryDecodeLD2_ASISDLSOP_H2_I2H(const InstData &data, Instruction &inst);

// LD2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD2_ASISDLSOP_HX2_R2H(const InstData &data, Instruction &inst);

// LD2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8
bool TryDecodeLD2_ASISDLSOP_S2_I2S(const InstData &data, Instruction &inst);

// LD2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD2_ASISDLSOP_SX2_R2S(const InstData &data, Instruction &inst);

// LD2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16
bool TryDecodeLD2_ASISDLSOP_D2_I2D(const InstData &data, Instruction &inst);

// LD2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD2_ASISDLSOP_DX2_R2D(const InstData &data, Instruction &inst);

// BR  <Xn>
bool TryDecodeBR_64_BRANCH_REG(const InstData &data, Instruction &inst);

// FCVTZU  <Hd>, <Hn>
bool TryDecodeFCVTZU_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTZU  <V><d>, <V><n>
bool TryDecodeFCVTZU_ASISDMISC_R(const InstData &data, Instruction &inst);

// FCVTZU  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTZU_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTZU  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTZU_ASIMDMISC_R(const InstData &data, Instruction &inst);

// MVN  <Wd>, <Wm>{, <shift> #<amount>}
bool TryDecodeMVN_ORN_32_LOG_SHIFT(const InstData &data, Instruction &inst);

// MVN  <Xd>, <Xm>{, <shift> #<amount>}
bool TryDecodeMVN_ORN_64_LOG_SHIFT(const InstData &data, Instruction &inst);

// STEOR  <Ws>, [<Xn|SP>]
bool TryDecodeSTEOR_32S_MEMOP(const InstData &data, Instruction &inst);

// STEORL  <Ws>, [<Xn|SP>]
bool TryDecodeSTEORL_32S_MEMOP(const InstData &data, Instruction &inst);

// STEOR  <Xs>, [<Xn|SP>]
bool TryDecodeSTEOR_64S_MEMOP(const InstData &data, Instruction &inst);

// STEORL  <Xs>, [<Xn|SP>]
bool TryDecodeSTEORL_64S_MEMOP(const InstData &data, Instruction &inst);

// TBX  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>
bool TryDecodeTBX_ASIMDTBL_L2_2(const InstData &data, Instruction &inst);

// TBX  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>
bool TryDecodeTBX_ASIMDTBL_L3_3(const InstData &data, Instruction &inst);

// TBX  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>
bool TryDecodeTBX_ASIMDTBL_L4_4(const InstData &data, Instruction &inst);

// TBX  <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>
bool TryDecodeTBX_ASIMDTBL_L1_1(const InstData &data, Instruction &inst);

// UMLAL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
bool TryDecodeUMLAL_ASIMDELEM_L(const InstData &data, Instruction &inst);

// UMINP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUMINP_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// CMLE  <V><d>, <V><n>, #0
bool TryDecodeCMLE_ASISDMISC_Z(const InstData &data, Instruction &inst);

// CMLE  <Vd>.<T>, <Vn>.<T>, #0
bool TryDecodeCMLE_ASIMDMISC_Z(const InstData &data, Instruction &inst);

// EOR  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeEOR_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// CMEQ  <V><d>, <V><n>, #0
bool TryDecodeCMEQ_ASISDMISC_Z(const InstData &data, Instruction &inst);

// CMEQ  <Vd>.<T>, <Vn>.<T>, #0
bool TryDecodeCMEQ_ASIMDMISC_Z(const InstData &data, Instruction &inst);

// LDUMAXAH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAXAH_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMAXALH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAXALH_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMAXH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAXH_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMAXLH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAXLH_32_MEMOP(const InstData &data, Instruction &inst);

// ST3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>]
bool TryDecodeST3_ASISDLSO_B3_3B(const InstData &data, Instruction &inst);

// ST3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>]
bool TryDecodeST3_ASISDLSO_H3_3H(const InstData &data, Instruction &inst);

// ST3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>]
bool TryDecodeST3_ASISDLSO_S3_3S(const InstData &data, Instruction &inst);

// ST3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>]
bool TryDecodeST3_ASISDLSO_D3_3D(const InstData &data, Instruction &inst);

// ST3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3
bool TryDecodeST3_ASISDLSOP_B3_I3B(const InstData &data, Instruction &inst);

// ST3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST3_ASISDLSOP_BX3_R3B(const InstData &data, Instruction &inst);

// ST3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6
bool TryDecodeST3_ASISDLSOP_H3_I3H(const InstData &data, Instruction &inst);

// ST3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST3_ASISDLSOP_HX3_R3H(const InstData &data, Instruction &inst);

// ST3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12
bool TryDecodeST3_ASISDLSOP_S3_I3S(const InstData &data, Instruction &inst);

// ST3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST3_ASISDLSOP_SX3_R3S(const InstData &data, Instruction &inst);

// ST3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24
bool TryDecodeST3_ASISDLSOP_D3_I3D(const InstData &data, Instruction &inst);

// ST3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST3_ASISDLSOP_DX3_R3D(const InstData &data, Instruction &inst);

// ASR  <Wd>, <Wn>, #<shift>
bool TryDecodeASR_SBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// ASR  <Xd>, <Xn>, #<shift>
bool TryDecodeASR_SBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// LDRSW  <Xt>, <label>
bool TryDecodeLDRSW_64_LOADLIT(const InstData &data, Instruction &inst);

// LDADDA  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADDA_32_MEMOP(const InstData &data, Instruction &inst);

// LDADDAL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADDAL_32_MEMOP(const InstData &data, Instruction &inst);

// LDADD  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADD_32_MEMOP(const InstData &data, Instruction &inst);

// LDADDL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADDL_32_MEMOP(const InstData &data, Instruction &inst);

// LDADDA  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDADDA_64_MEMOP(const InstData &data, Instruction &inst);

// LDADDAL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDADDAL_64_MEMOP(const InstData &data, Instruction &inst);

// LDADD  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDADD_64_MEMOP(const InstData &data, Instruction &inst);

// LDADDL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDADDL_64_MEMOP(const InstData &data, Instruction &inst);

// FCVTZS  <V><d>, <V><n>, #<fbits>
bool TryDecodeFCVTZS_ASISDSHF_C(const InstData &data, Instruction &inst);

// FCVTZS  <Vd>.<T>, <Vn>.<T>, #<fbits>
bool TryDecodeFCVTZS_ASIMDSHF_C(const InstData &data, Instruction &inst);

// LSR  <Wd>, <Wn>, #<shift>
bool TryDecodeLSR_UBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// LSR  <Xd>, <Xn>, #<shift>
bool TryDecodeLSR_UBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// ST2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>]
bool TryDecodeST2_ASISDLSO_B2_2B(const InstData &data, Instruction &inst);

// ST2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>]
bool TryDecodeST2_ASISDLSO_H2_2H(const InstData &data, Instruction &inst);

// ST2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>]
bool TryDecodeST2_ASISDLSO_S2_2S(const InstData &data, Instruction &inst);

// ST2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>]
bool TryDecodeST2_ASISDLSO_D2_2D(const InstData &data, Instruction &inst);

// ST2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2
bool TryDecodeST2_ASISDLSOP_B2_I2B(const InstData &data, Instruction &inst);

// ST2  { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST2_ASISDLSOP_BX2_R2B(const InstData &data, Instruction &inst);

// ST2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4
bool TryDecodeST2_ASISDLSOP_H2_I2H(const InstData &data, Instruction &inst);

// ST2  { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST2_ASISDLSOP_HX2_R2H(const InstData &data, Instruction &inst);

// ST2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8
bool TryDecodeST2_ASISDLSOP_S2_I2S(const InstData &data, Instruction &inst);

// ST2  { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST2_ASISDLSOP_SX2_R2S(const InstData &data, Instruction &inst);

// ST2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16
bool TryDecodeST2_ASISDLSOP_D2_I2D(const InstData &data, Instruction &inst);

// ST2  { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST2_ASISDLSOP_DX2_R2D(const InstData &data, Instruction &inst);

// RADDHN{2}  <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>
bool TryDecodeRADDHN_ASIMDDIFF_N(const InstData &data, Instruction &inst);

// STUR  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTUR_32_LDST_UNSCALED(const InstData &data, Instruction &inst);

// STUR  <Xt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTUR_64_LDST_UNSCALED(const InstData &data, Instruction &inst);

// CLS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeCLS_ASIMDMISC_R(const InstData &data, Instruction &inst);

// SADDL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeSADDL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// ADDP  <V><d>, <Vn>.<T>
bool TryDecodeADDP_ASISDPAIR_ONLY(const InstData &data, Instruction &inst);

// CMP  <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeCMP_SUBS_32_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// CMP  <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeCMP_SUBS_64_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// STR  <Bt>, [<Xn|SP>], #<simm>
bool TryDecodeSTR_B_LDST_IMMPOST(const InstData &data, Instruction &inst);

// STR  <Ht>, [<Xn|SP>], #<simm>
bool TryDecodeSTR_H_LDST_IMMPOST(const InstData &data, Instruction &inst);

// STR  <St>, [<Xn|SP>], #<simm>
bool TryDecodeSTR_S_LDST_IMMPOST(const InstData &data, Instruction &inst);

// STR  <Dt>, [<Xn|SP>], #<simm>
bool TryDecodeSTR_D_LDST_IMMPOST(const InstData &data, Instruction &inst);

// STR  <Qt>, [<Xn|SP>], #<simm>
bool TryDecodeSTR_Q_LDST_IMMPOST(const InstData &data, Instruction &inst);

// STR  <Bt>, [<Xn|SP>, #<simm>]!
bool TryDecodeSTR_B_LDST_IMMPRE(const InstData &data, Instruction &inst);

// STR  <Ht>, [<Xn|SP>, #<simm>]!
bool TryDecodeSTR_H_LDST_IMMPRE(const InstData &data, Instruction &inst);

// STR  <St>, [<Xn|SP>, #<simm>]!
bool TryDecodeSTR_S_LDST_IMMPRE(const InstData &data, Instruction &inst);

// STR  <Dt>, [<Xn|SP>, #<simm>]!
bool TryDecodeSTR_D_LDST_IMMPRE(const InstData &data, Instruction &inst);

// STR  <Qt>, [<Xn|SP>, #<simm>]!
bool TryDecodeSTR_Q_LDST_IMMPRE(const InstData &data, Instruction &inst);

// STR  <Bt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeSTR_B_LDST_POS(const InstData &data, Instruction &inst);

// STR  <Ht>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeSTR_H_LDST_POS(const InstData &data, Instruction &inst);

// STR  <St>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeSTR_S_LDST_POS(const InstData &data, Instruction &inst);

// STR  <Dt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeSTR_D_LDST_POS(const InstData &data, Instruction &inst);

// STR  <Qt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeSTR_Q_LDST_POS(const InstData &data, Instruction &inst);

// LDSETAB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSETAB_32_MEMOP(const InstData &data, Instruction &inst);

// LDSETALB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSETALB_32_MEMOP(const InstData &data, Instruction &inst);

// LDSETB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSETB_32_MEMOP(const InstData &data, Instruction &inst);

// LDSETLB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSETLB_32_MEMOP(const InstData &data, Instruction &inst);

// MOV  <Wd>, <Wm>
bool TryDecodeMOV_ORR_32_LOG_SHIFT(const InstData &data, Instruction &inst);

// MOV  <Xd>, <Xm>
bool TryDecodeMOV_ORR_64_LOG_SHIFT(const InstData &data, Instruction &inst);

// FRINTP  <Hd>, <Hn>
bool TryDecodeFRINTP_H_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTP  <Sd>, <Sn>
bool TryDecodeFRINTP_S_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTP  <Dd>, <Dn>
bool TryDecodeFRINTP_D_FLOATDP1(const InstData &data, Instruction &inst);

// CASA  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCASA_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASAL  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCASAL_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// CAS  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCAS_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASL  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCASL_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASA  <Xs>, <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeCASA_C64_LDSTEXCL(const InstData &data, Instruction &inst);

// CASAL  <Xs>, <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeCASAL_C64_LDSTEXCL(const InstData &data, Instruction &inst);

// CAS  <Xs>, <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeCAS_C64_LDSTEXCL(const InstData &data, Instruction &inst);

// CASL  <Xs>, <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeCASL_C64_LDSTEXCL(const InstData &data, Instruction &inst);

// WFE
bool TryDecodeWFE_HI_SYSTEM(const InstData &data, Instruction &inst);

// LDUMINA  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMINA_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMINAL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMINAL_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMIN  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMIN_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMINL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMINL_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMINA  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDUMINA_64_MEMOP(const InstData &data, Instruction &inst);

// LDUMINAL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDUMINAL_64_MEMOP(const InstData &data, Instruction &inst);

// LDUMIN  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDUMIN_64_MEMOP(const InstData &data, Instruction &inst);

// LDUMINL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDUMINL_64_MEMOP(const InstData &data, Instruction &inst);

// STXRB  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTXRB_SR32_LDSTEXCL(const InstData &data, Instruction &inst);

// STLXRH  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLXRH_SR32_LDSTEXCL(const InstData &data, Instruction &inst);

// STLLRH  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLLRH_SL32_LDSTEXCL(const InstData &data, Instruction &inst);

// LDUMINAH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMINAH_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMINALH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMINALH_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMINH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMINH_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMINLH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMINLH_32_MEMOP(const InstData &data, Instruction &inst);

// LSLV  <Wd>, <Wn>, <Wm>
bool TryDecodeLSLV_32_DP_2SRC(const InstData &data, Instruction &inst);

// LSLV  <Xd>, <Xn>, <Xm>
bool TryDecodeLSLV_64_DP_2SRC(const InstData &data, Instruction &inst);

// INS  <Vd>.<Ts>[<index>], <R><n>
bool TryDecodeINS_ASIMDINS_IR_R(const InstData &data, Instruction &inst);

// CMGT  <V><d>, <V><n>, #0
bool TryDecodeCMGT_ASISDMISC_Z(const InstData &data, Instruction &inst);

// CMGT  <Vd>.<T>, <Vn>.<T>, #0
bool TryDecodeCMGT_ASIMDMISC_Z(const InstData &data, Instruction &inst);

// SMLAL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
bool TryDecodeSMLAL_ASIMDELEM_L(const InstData &data, Instruction &inst);

// STCLR  <Ws>, [<Xn|SP>]
bool TryDecodeSTCLR_32S_MEMOP(const InstData &data, Instruction &inst);

// STCLRL  <Ws>, [<Xn|SP>]
bool TryDecodeSTCLRL_32S_MEMOP(const InstData &data, Instruction &inst);

// STCLR  <Xs>, [<Xn|SP>]
bool TryDecodeSTCLR_64S_MEMOP(const InstData &data, Instruction &inst);

// STCLRL  <Xs>, [<Xn|SP>]
bool TryDecodeSTCLRL_64S_MEMOP(const InstData &data, Instruction &inst);

// BIT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeBIT_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// CMEQ  <V><d>, <V><n>, <V><m>
bool TryDecodeCMEQ_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// CMEQ  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeCMEQ_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// CRC32CB  <Wd>, <Wn>, <Wm>
bool TryDecodeCRC32CB_32C_DP_2SRC(const InstData &data, Instruction &inst);

// CRC32CH  <Wd>, <Wn>, <Wm>
bool TryDecodeCRC32CH_32C_DP_2SRC(const InstData &data, Instruction &inst);

// CRC32CW  <Wd>, <Wn>, <Wm>
bool TryDecodeCRC32CW_32C_DP_2SRC(const InstData &data, Instruction &inst);

// CRC32CX  <Wd>, <Wn>, <Xm>
bool TryDecodeCRC32CX_64C_DP_2SRC(const InstData &data, Instruction &inst);

// STRH  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeSTRH_32_LDST_REGOFF(const InstData &data, Instruction &inst);

// BRK  #<imm>
bool TryDecodeBRK_EX_EXCEPTION(const InstData &data, Instruction &inst);

// UADDLP  <Vd>.<Ta>, <Vn>.<Tb>
bool TryDecodeUADDLP_ASIMDMISC_P(const InstData &data, Instruction &inst);

// UMAXV  <V><d>, <Vn>.<T>
bool TryDecodeUMAXV_ASIMDALL_ONLY(const InstData &data, Instruction &inst);

// LDEORAH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEORAH_32_MEMOP(const InstData &data, Instruction &inst);

// LDEORALH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEORALH_32_MEMOP(const InstData &data, Instruction &inst);

// LDEORH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEORH_32_MEMOP(const InstData &data, Instruction &inst);

// LDEORLH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEORLH_32_MEMOP(const InstData &data, Instruction &inst);

// SMAXV  <V><d>, <Vn>.<T>
bool TryDecodeSMAXV_ASIMDALL_ONLY(const InstData &data, Instruction &inst);

// XTN{2}  <Vd>.<Tb>, <Vn>.<Ta>
bool TryDecodeXTN_ASIMDMISC_N(const InstData &data, Instruction &inst);

// STRB  <Wt>, [<Xn|SP>], #<simm>
bool TryDecodeSTRB_32_LDST_IMMPOST(const InstData &data, Instruction &inst);

// STRB  <Wt>, [<Xn|SP>, #<simm>]!
bool TryDecodeSTRB_32_LDST_IMMPRE(const InstData &data, Instruction &inst);

// STRB  <Wt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeSTRB_32_LDST_POS(const InstData &data, Instruction &inst);

// USQADD  <V><d>, <V><n>
bool TryDecodeUSQADD_ASISDMISC_R(const InstData &data, Instruction &inst);

// USQADD  <Vd>.<T>, <Vn>.<T>
bool TryDecodeUSQADD_ASIMDMISC_R(const InstData &data, Instruction &inst);

// FCVTZS  <Wd>, <Hn>, #<fbits>
bool TryDecodeFCVTZS_32H_FLOAT2FIX(const InstData &data, Instruction &inst);

// FCVTZS  <Xd>, <Hn>, #<fbits>
bool TryDecodeFCVTZS_64H_FLOAT2FIX(const InstData &data, Instruction &inst);

// FCVTZS  <Wd>, <Sn>, #<fbits>
bool TryDecodeFCVTZS_32S_FLOAT2FIX(const InstData &data, Instruction &inst);

// FCVTZS  <Xd>, <Sn>, #<fbits>
bool TryDecodeFCVTZS_64S_FLOAT2FIX(const InstData &data, Instruction &inst);

// FCVTZS  <Wd>, <Dn>, #<fbits>
bool TryDecodeFCVTZS_32D_FLOAT2FIX(const InstData &data, Instruction &inst);

// FCVTZS  <Xd>, <Dn>, #<fbits>
bool TryDecodeFCVTZS_64D_FLOAT2FIX(const InstData &data, Instruction &inst);

// UQADD  <V><d>, <V><n>, <V><m>
bool TryDecodeUQADD_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// UQADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUQADD_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// LDR  <Wt>, <label>
bool TryDecodeLDR_32_LOADLIT(const InstData &data, Instruction &inst);

// LDR  <Xt>, <label>
bool TryDecodeLDR_64_LOADLIT(const InstData &data, Instruction &inst);

// FNMSUB  <Hd>, <Hn>, <Hm>, <Ha>
bool TryDecodeFNMSUB_H_FLOATDP3(const InstData &data, Instruction &inst);

// FNMSUB  <Sd>, <Sn>, <Sm>, <Sa>
bool TryDecodeFNMSUB_S_FLOATDP3(const InstData &data, Instruction &inst);

// FNMSUB  <Dd>, <Dn>, <Dm>, <Da>
bool TryDecodeFNMSUB_D_FLOATDP3(const InstData &data, Instruction &inst);

// ADDP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeADDP_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SHA1M  <Qd>, <Sn>, <Vm>.4S
bool TryDecodeSHA1M_QSV_CRYPTOSHA3(const InstData &data, Instruction &inst);

// LDAXP  <Wt1>, <Wt2>, [<Xn|SP>{,#0}]
bool TryDecodeLDAXP_LP32_LDSTEXCL(const InstData &data, Instruction &inst);

// LDAXP  <Xt1>, <Xt2>, [<Xn|SP>{,#0}]
bool TryDecodeLDAXP_LP64_LDSTEXCL(const InstData &data, Instruction &inst);

// CASPA  <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{,#0}]
bool TryDecodeCASPA_CP32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASPAL  <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{,#0}]
bool TryDecodeCASPAL_CP32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASP  <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{,#0}]
bool TryDecodeCASP_CP32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASPL  <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{,#0}]
bool TryDecodeCASPL_CP32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASPA  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{,#0}]
bool TryDecodeCASPA_CP64_LDSTEXCL(const InstData &data, Instruction &inst);

// CASPAL  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{,#0}]
bool TryDecodeCASPAL_CP64_LDSTEXCL(const InstData &data, Instruction &inst);

// CASP  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{,#0}]
bool TryDecodeCASP_CP64_LDSTEXCL(const InstData &data, Instruction &inst);

// CASPL  <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{,#0}]
bool TryDecodeCASPL_CP64_LDSTEXCL(const InstData &data, Instruction &inst);

// FCVTZU  <Wd>, <Hn>, #<fbits>
bool TryDecodeFCVTZU_32H_FLOAT2FIX(const InstData &data, Instruction &inst);

// FCVTZU  <Xd>, <Hn>, #<fbits>
bool TryDecodeFCVTZU_64H_FLOAT2FIX(const InstData &data, Instruction &inst);

// FCVTZU  <Wd>, <Sn>, #<fbits>
bool TryDecodeFCVTZU_32S_FLOAT2FIX(const InstData &data, Instruction &inst);

// FCVTZU  <Xd>, <Sn>, #<fbits>
bool TryDecodeFCVTZU_64S_FLOAT2FIX(const InstData &data, Instruction &inst);

// FCVTZU  <Wd>, <Dn>, #<fbits>
bool TryDecodeFCVTZU_32D_FLOAT2FIX(const InstData &data, Instruction &inst);

// FCVTZU  <Xd>, <Dn>, #<fbits>
bool TryDecodeFCVTZU_64D_FLOAT2FIX(const InstData &data, Instruction &inst);

// SHA1P  <Qd>, <Sn>, <Vm>.4S
bool TryDecodeSHA1P_QSV_CRYPTOSHA3(const InstData &data, Instruction &inst);

// SADDLV  <V><d>, <Vn>.<T>
bool TryDecodeSADDLV_ASIMDALL_ONLY(const InstData &data, Instruction &inst);

// TBL  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>
bool TryDecodeTBL_ASIMDTBL_L2_2(const InstData &data, Instruction &inst);

// TBL  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>
bool TryDecodeTBL_ASIMDTBL_L3_3(const InstData &data, Instruction &inst);

// TBL  <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>
bool TryDecodeTBL_ASIMDTBL_L4_4(const InstData &data, Instruction &inst);

// TBL  <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>
bool TryDecodeTBL_ASIMDTBL_L1_1(const InstData &data, Instruction &inst);

// ADD  <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
bool TryDecodeADD_32_ADDSUB_EXT(const InstData &data, Instruction &inst);

// ADD  <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
bool TryDecodeADD_64_ADDSUB_EXT(const InstData &data, Instruction &inst);

// FMAXNMP  <V><d>, <Vn>.<T>
bool TryDecodeFMAXNMP_ASISDPAIR_ONLY_H(const InstData &data, Instruction &inst);

// FMAXNMP  <V><d>, <Vn>.<T>
bool TryDecodeFMAXNMP_ASISDPAIR_ONLY_SD(const InstData &data,
                                        Instruction &inst);

// BICS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeBICS_32_LOG_SHIFT(const InstData &data, Instruction &inst);

// BICS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeBICS_64_LOG_SHIFT(const InstData &data, Instruction &inst);

// FNMUL  <Hd>, <Hn>, <Hm>
bool TryDecodeFNMUL_H_FLOATDP2(const InstData &data, Instruction &inst);

// FNMUL  <Sd>, <Sn>, <Sm>
bool TryDecodeFNMUL_S_FLOATDP2(const InstData &data, Instruction &inst);

// FNMUL  <Dd>, <Dn>, <Dm>
bool TryDecodeFNMUL_D_FLOATDP2(const InstData &data, Instruction &inst);

// SQSUB  <V><d>, <V><n>, <V><m>
bool TryDecodeSQSUB_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// SQSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSQSUB_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SQXTN  <Vb><d>, <Va><n>
bool TryDecodeSQXTN_ASISDMISC_N(const InstData &data, Instruction &inst);

// SQXTN{2}  <Vd>.<Tb>, <Vn>.<Ta>
bool TryDecodeSQXTN_ASIMDMISC_N(const InstData &data, Instruction &inst);

// MOV  <Vd>.<T>, <Vn>.<T>
bool TryDecodeMOV_ORR_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// REV64  <Xd>, <Xn>
bool TryDecodeREV64_REV_64_DP_1SRC(const InstData &data, Instruction &inst);

// STLXRB  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLXRB_SR32_LDSTEXCL(const InstData &data, Instruction &inst);

// STTRH  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTTRH_32_LDST_UNPRIV(const InstData &data, Instruction &inst);

// SMINP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSMINP_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SHA256SU1  <Vd>.4S, <Vn>.4S, <Vm>.4S
bool TryDecodeSHA256SU1_VVV_CRYPTOSHA3(const InstData &data, Instruction &inst);

// FMSUB  <Hd>, <Hn>, <Hm>, <Ha>
bool TryDecodeFMSUB_H_FLOATDP3(const InstData &data, Instruction &inst);

// FMSUB  <Sd>, <Sn>, <Sm>, <Sa>
bool TryDecodeFMSUB_S_FLOATDP3(const InstData &data, Instruction &inst);

// FMSUB  <Dd>, <Dn>, <Dm>, <Da>
bool TryDecodeFMSUB_D_FLOATDP3(const InstData &data, Instruction &inst);

// NGCS  <Wd>, <Wm>
bool TryDecodeNGCS_SBCS_32_ADDSUB_CARRY(const InstData &data,
                                        Instruction &inst);

// NGCS  <Xd>, <Xm>
bool TryDecodeNGCS_SBCS_64_ADDSUB_CARRY(const InstData &data,
                                        Instruction &inst);

// STR  <Wt>, [<Xn|SP>], #<simm>
bool TryDecodeSTR_32_LDST_IMMPOST(const InstData &data, Instruction &inst);

// STR  <Xt>, [<Xn|SP>], #<simm>
bool TryDecodeSTR_64_LDST_IMMPOST(const InstData &data, Instruction &inst);

// STR  <Wt>, [<Xn|SP>, #<simm>]!
bool TryDecodeSTR_32_LDST_IMMPRE(const InstData &data, Instruction &inst);

// STR  <Xt>, [<Xn|SP>, #<simm>]!
bool TryDecodeSTR_64_LDST_IMMPRE(const InstData &data, Instruction &inst);

// STR  <Wt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeSTR_32_LDST_POS(const InstData &data, Instruction &inst);

// STR  <Xt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeSTR_64_LDST_POS(const InstData &data, Instruction &inst);

// INS  <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]
bool TryDecodeINS_ASIMDINS_IV_V(const InstData &data, Instruction &inst);

// DCPS2  {#<imm>}
bool TryDecodeDCPS2_DC_EXCEPTION(const InstData &data, Instruction &inst);

// TST  <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeTST_ANDS_32_LOG_SHIFT(const InstData &data, Instruction &inst);

// TST  <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeTST_ANDS_64_LOG_SHIFT(const InstData &data, Instruction &inst);

// DCPS1  {#<imm>}
bool TryDecodeDCPS1_DC_EXCEPTION(const InstData &data, Instruction &inst);

// FMLA  <Hd>, <Hn>, <Vm>.H[<index>]
bool TryDecodeFMLA_ASISDELEM_RH_H(const InstData &data, Instruction &inst);

// FMLA  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
bool TryDecodeFMLA_ASISDELEM_R_SD(const InstData &data, Instruction &inst);

// FMLA  <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>]
bool TryDecodeFMLA_ASIMDELEM_RH_H(const InstData &data, Instruction &inst);

// FMLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
bool TryDecodeFMLA_ASIMDELEM_R_SD(const InstData &data, Instruction &inst);

// SCVTF  <Hd>, <Hn>
bool TryDecodeSCVTF_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// SCVTF  <V><d>, <V><n>
bool TryDecodeSCVTF_ASISDMISC_R(const InstData &data, Instruction &inst);

// SCVTF  <Vd>.<T>, <Vn>.<T>
bool TryDecodeSCVTF_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// SCVTF  <Vd>.<T>, <Vn>.<T>
bool TryDecodeSCVTF_ASIMDMISC_R(const InstData &data, Instruction &inst);

// UMULL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeUMULL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// FMUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMUL_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FMUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMUL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FMLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMLA_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FMLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMLA_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SDIV  <Wd>, <Wn>, <Wm>
bool TryDecodeSDIV_32_DP_2SRC(const InstData &data, Instruction &inst);

// SDIV  <Xd>, <Xn>, <Xm>
bool TryDecodeSDIV_64_DP_2SRC(const InstData &data, Instruction &inst);

// ADD  <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
bool TryDecodeADD_32_ADDSUB_IMM(const InstData &data, Instruction &inst);

// ADD  <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
bool TryDecodeADD_64_ADDSUB_IMM(const InstData &data, Instruction &inst);

// RBIT  <Wd>, <Wn>
bool TryDecodeRBIT_32_DP_1SRC(const InstData &data, Instruction &inst);

// RBIT  <Xd>, <Xn>
bool TryDecodeRBIT_64_DP_1SRC(const InstData &data, Instruction &inst);

// SMNEGL  <Xd>, <Wn>, <Wm>
bool TryDecodeSMNEGL_SMSUBL_64WA_DP_3SRC(const InstData &data,
                                         Instruction &inst);

// MOV  <V><d>, <Vn>.<T>[<index>]
bool TryDecodeMOV_DUP_ASISDONE_ONLY(const InstData &data, Instruction &inst);

// SMULL  <Xd>, <Wn>, <Wm>
bool TryDecodeSMULL_SMADDL_64WA_DP_3SRC(const InstData &data,
                                        Instruction &inst);

// ZIP2  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeZIP2_ASIMDPERM_ONLY(const InstData &data, Instruction &inst);

// LDAXRB  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDAXRB_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// MNEG  <Wd>, <Wn>, <Wm>
bool TryDecodeMNEG_MSUB_32A_DP_3SRC(const InstData &data, Instruction &inst);

// MNEG  <Xd>, <Xn>, <Xm>
bool TryDecodeMNEG_MSUB_64A_DP_3SRC(const InstData &data, Instruction &inst);

// HVC  #<imm>
bool TryDecodeHVC_EX_EXCEPTION(const InstData &data, Instruction &inst);

// DCPS3  {#<imm>}
bool TryDecodeDCPS3_DC_EXCEPTION(const InstData &data, Instruction &inst);

// FCVTNU  <Hd>, <Hn>
bool TryDecodeFCVTNU_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTNU  <V><d>, <V><n>
bool TryDecodeFCVTNU_ASISDMISC_R(const InstData &data, Instruction &inst);

// FCVTNU  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTNU_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTNU  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTNU_ASIMDMISC_R(const InstData &data, Instruction &inst);

// STUMINB  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMINB_32S_MEMOP(const InstData &data, Instruction &inst);

// STUMINLB  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMINLB_32S_MEMOP(const InstData &data, Instruction &inst);

// TBNZ  <R><t>, #<imm>, <label>
bool TryDecodeTBNZ_ONLY_TESTBRANCH(const InstData &data, Instruction &inst);

// STCLRH  <Ws>, [<Xn|SP>]
bool TryDecodeSTCLRH_32S_MEMOP(const InstData &data, Instruction &inst);

// STCLRLH  <Ws>, [<Xn|SP>]
bool TryDecodeSTCLRLH_32S_MEMOP(const InstData &data, Instruction &inst);

// BL  <label>
bool TryDecodeBL_ONLY_BRANCH_IMM(const InstData &data, Instruction &inst);

// FCVTMU  <Hd>, <Hn>
bool TryDecodeFCVTMU_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTMU  <V><d>, <V><n>
bool TryDecodeFCVTMU_ASISDMISC_R(const InstData &data, Instruction &inst);

// FCVTMU  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTMU_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTMU  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTMU_ASIMDMISC_R(const InstData &data, Instruction &inst);

// FMAXNMP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMAXNMP_ASIMDSAMEFP16_ONLY(const InstData &data,
                                         Instruction &inst);

// FMAXNMP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMAXNMP_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FMOV  <Wd>, <Hn>
bool TryDecodeFMOV_32H_FLOAT2INT(const InstData &data, Instruction &inst);

// FMOV  <Xd>, <Hn>
bool TryDecodeFMOV_64H_FLOAT2INT(const InstData &data, Instruction &inst);

// FMOV  <Hd>, <Wn>
bool TryDecodeFMOV_H32_FLOAT2INT(const InstData &data, Instruction &inst);

// FMOV  <Sd>, <Wn>
bool TryDecodeFMOV_S32_FLOAT2INT(const InstData &data, Instruction &inst);

// FMOV  <Wd>, <Sn>
bool TryDecodeFMOV_32S_FLOAT2INT(const InstData &data, Instruction &inst);

// FMOV  <Hd>, <Xn>
bool TryDecodeFMOV_H64_FLOAT2INT(const InstData &data, Instruction &inst);

// FMOV  <Dd>, <Xn>
bool TryDecodeFMOV_D64_FLOAT2INT(const InstData &data, Instruction &inst);

// FMOV  <Vd>.D[1], <Xn>
bool TryDecodeFMOV_V64I_FLOAT2INT(const InstData &data, Instruction &inst);

// FMOV  <Xd>, <Dn>
bool TryDecodeFMOV_64D_FLOAT2INT(const InstData &data, Instruction &inst);

// FMOV  <Xd>, <Vn>.D[1]
bool TryDecodeFMOV_64VX_FLOAT2INT(const InstData &data, Instruction &inst);

// LDCLRAH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLRAH_32_MEMOP(const InstData &data, Instruction &inst);

// LDCLRALH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLRALH_32_MEMOP(const InstData &data, Instruction &inst);

// LDCLRH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLRH_32_MEMOP(const InstData &data, Instruction &inst);

// LDCLRLH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLRLH_32_MEMOP(const InstData &data, Instruction &inst);

// SABAL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeSABAL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// LDSETA  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSETA_32_MEMOP(const InstData &data, Instruction &inst);

// LDSETAL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSETAL_32_MEMOP(const InstData &data, Instruction &inst);

// LDSET  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSET_32_MEMOP(const InstData &data, Instruction &inst);

// LDSETL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSETL_32_MEMOP(const InstData &data, Instruction &inst);

// LDSETA  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSETA_64_MEMOP(const InstData &data, Instruction &inst);

// LDSETAL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSETAL_64_MEMOP(const InstData &data, Instruction &inst);

// LDSET  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSET_64_MEMOP(const InstData &data, Instruction &inst);

// LDSETL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSETL_64_MEMOP(const InstData &data, Instruction &inst);

// FRECPS  <Hd>, <Hn>, <Hm>
bool TryDecodeFRECPS_ASISDSAMEFP16_ONLY(const InstData &data,
                                        Instruction &inst);

// FRECPS  <V><d>, <V><n>, <V><m>
bool TryDecodeFRECPS_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// FRECPS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFRECPS_ASIMDSAMEFP16_ONLY(const InstData &data,
                                        Instruction &inst);

// FRECPS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFRECPS_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SMLAL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeSMLAL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// LDSMINAH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMINAH_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMINALH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMINALH_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMINH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMINH_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMINLH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMINLH_32_MEMOP(const InstData &data, Instruction &inst);

// FRINTI  <Hd>, <Hn>
bool TryDecodeFRINTI_H_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTI  <Sd>, <Sn>
bool TryDecodeFRINTI_S_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTI  <Dd>, <Dn>
bool TryDecodeFRINTI_D_FLOATDP1(const InstData &data, Instruction &inst);

// SMULH  <Xd>, <Xn>, <Xm>
bool TryDecodeSMULH_64_DP_3SRC(const InstData &data, Instruction &inst);

// FMADD  <Hd>, <Hn>, <Hm>, <Ha>
bool TryDecodeFMADD_H_FLOATDP3(const InstData &data, Instruction &inst);

// FMADD  <Sd>, <Sn>, <Sm>, <Sa>
bool TryDecodeFMADD_S_FLOATDP3(const InstData &data, Instruction &inst);

// FMADD  <Dd>, <Dn>, <Dm>, <Da>
bool TryDecodeFMADD_D_FLOATDP3(const InstData &data, Instruction &inst);

// CCMP  <Wn>, <Wm>, #<nzcv>, <cond>
bool TryDecodeCCMP_32_CONDCMP_REG(const InstData &data, Instruction &inst);

// CCMP  <Xn>, <Xm>, #<nzcv>, <cond>
bool TryDecodeCCMP_64_CONDCMP_REG(const InstData &data, Instruction &inst);

// SRSHL  <V><d>, <V><n>, <V><m>
bool TryDecodeSRSHL_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// SRSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSRSHL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FADD  <Hd>, <Hn>, <Hm>
bool TryDecodeFADD_H_FLOATDP2(const InstData &data, Instruction &inst);

// FADD  <Sd>, <Sn>, <Sm>
bool TryDecodeFADD_S_FLOATDP2(const InstData &data, Instruction &inst);

// FADD  <Dd>, <Dn>, <Dm>
bool TryDecodeFADD_D_FLOATDP2(const InstData &data, Instruction &inst);

// FMULX  <Hd>, <Hn>, <Vm>.H[<index>]
bool TryDecodeFMULX_ASISDELEM_RH_H(const InstData &data, Instruction &inst);

// FMULX  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
bool TryDecodeFMULX_ASISDELEM_R_SD(const InstData &data, Instruction &inst);

// FMULX  <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>]
bool TryDecodeFMULX_ASIMDELEM_RH_H(const InstData &data, Instruction &inst);

// FMULX  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
bool TryDecodeFMULX_ASIMDELEM_R_SD(const InstData &data, Instruction &inst);

// BIC  <Vd>.<T>, #<imm8>{, LSL #<amount>}
bool TryDecodeBIC_ASIMDIMM_L_HL(const InstData &data, Instruction &inst);

// BIC  <Vd>.<T>, #<imm8>{, LSL #<amount>}
bool TryDecodeBIC_ASIMDIMM_L_SL(const InstData &data, Instruction &inst);

// DC  <dc_op>, <Xt>
bool TryDecodeDC_SYS_CR_SYSTEM(const InstData &data, Instruction &inst);

// PRFM  (<prfop>|#<imm5>), [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodePRFM_P_LDST_REGOFF(const InstData &data, Instruction &inst);

// STUMINH  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMINH_32S_MEMOP(const InstData &data, Instruction &inst);

// STUMINLH  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMINLH_32S_MEMOP(const InstData &data, Instruction &inst);

// ORR  <Vd>.<T>, #<imm8>{, LSL #<amount>}
bool TryDecodeORR_ASIMDIMM_L_HL(const InstData &data, Instruction &inst);

// ORR  <Vd>.<T>, #<imm8>{, LSL #<amount>}
bool TryDecodeORR_ASIMDIMM_L_SL(const InstData &data, Instruction &inst);

// FCVTAU  <Wd>, <Hn>
bool TryDecodeFCVTAU_32H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTAU  <Xd>, <Hn>
bool TryDecodeFCVTAU_64H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTAU  <Wd>, <Sn>
bool TryDecodeFCVTAU_32S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTAU  <Xd>, <Sn>
bool TryDecodeFCVTAU_64S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTAU  <Wd>, <Dn>
bool TryDecodeFCVTAU_32D_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTAU  <Xd>, <Dn>
bool TryDecodeFCVTAU_64D_FLOAT2INT(const InstData &data, Instruction &inst);

// LDXR  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDXR_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// LDXR  <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeLDXR_LR64_LDSTEXCL(const InstData &data, Instruction &inst);

// TLBI  <tlbi_op>{, <Xt>}
bool TryDecodeTLBI_SYS_CR_SYSTEM(const InstData &data, Instruction &inst);

// SVC  #<imm>
bool TryDecodeSVC_EX_EXCEPTION(const InstData &data, Instruction &inst);

// FCMPE  <Hn>, <Hm>
bool TryDecodeFCMPE_H_FLOATCMP(const InstData &data, Instruction &inst);

// FCMPE  <Hn>, #0.0
bool TryDecodeFCMPE_HZ_FLOATCMP(const InstData &data, Instruction &inst);

// FCMPE  <Sn>, <Sm>
bool TryDecodeFCMPE_S_FLOATCMP(const InstData &data, Instruction &inst);

// FCMPE  <Sn>, #0.0
bool TryDecodeFCMPE_SZ_FLOATCMP(const InstData &data, Instruction &inst);

// FCMPE  <Dn>, <Dm>
bool TryDecodeFCMPE_D_FLOATCMP(const InstData &data, Instruction &inst);

// FCMPE  <Dn>, #0.0
bool TryDecodeFCMPE_DZ_FLOATCMP(const InstData &data, Instruction &inst);

// FRSQRTS  <Hd>, <Hn>, <Hm>
bool TryDecodeFRSQRTS_ASISDSAMEFP16_ONLY(const InstData &data,
                                         Instruction &inst);

// FRSQRTS  <V><d>, <V><n>, <V><m>
bool TryDecodeFRSQRTS_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// FRSQRTS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFRSQRTS_ASIMDSAMEFP16_ONLY(const InstData &data,
                                         Instruction &inst);

// FRSQRTS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFRSQRTS_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FRINTN  <Hd>, <Hn>
bool TryDecodeFRINTN_H_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTN  <Sd>, <Sn>
bool TryDecodeFRINTN_S_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTN  <Dd>, <Dn>
bool TryDecodeFRINTN_D_FLOATDP1(const InstData &data, Instruction &inst);

// FMOV  <Hd>, #<imm>
bool TryDecodeFMOV_H_FLOATIMM(const InstData &data, Instruction &inst);

// FMOV  <Sd>, #<imm>
bool TryDecodeFMOV_S_FLOATIMM(const InstData &data, Instruction &inst);

// FMOV  <Dd>, #<imm>
bool TryDecodeFMOV_D_FLOATIMM(const InstData &data, Instruction &inst);

// EOR  <Wd|WSP>, <Wn>, #<imm>
bool TryDecodeEOR_32_LOG_IMM(const InstData &data, Instruction &inst);

// EOR  <Xd|SP>, <Xn>, #<imm>
bool TryDecodeEOR_64_LOG_IMM(const InstData &data, Instruction &inst);

// MRS  <Xt>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>)
bool TryDecodeMRS_RS_SYSTEM(const InstData &data, Instruction &inst);

// ESB
bool TryDecodeESB_HI_SYSTEM(const InstData &data, Instruction &inst);

// FCMLT  <Hd>, <Hn>, #0.0
bool TryDecodeFCMLT_ASISDMISCFP16_FZ(const InstData &data, Instruction &inst);

// FCMLT  <V><d>, <V><n>, #0.0
bool TryDecodeFCMLT_ASISDMISC_FZ(const InstData &data, Instruction &inst);

// FCMLT  <Vd>.<T>, <Vn>.<T>, #0.0
bool TryDecodeFCMLT_ASIMDMISCFP16_FZ(const InstData &data, Instruction &inst);

// FCMLT  <Vd>.<T>, <Vn>.<T>, #0.0
bool TryDecodeFCMLT_ASIMDMISC_FZ(const InstData &data, Instruction &inst);

// SQRDMULH  <V><d>, <V><n>, <V><m>
bool TryDecodeSQRDMULH_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// SQRDMULH  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSQRDMULH_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SWPAH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWPAH_32_MEMOP(const InstData &data, Instruction &inst);

// SWPALH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWPALH_32_MEMOP(const InstData &data, Instruction &inst);

// SWPH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWPH_32_MEMOP(const InstData &data, Instruction &inst);

// SWPLH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWPLH_32_MEMOP(const InstData &data, Instruction &inst);

// DUP  <V><d>, <Vn>.<T>[<index>]
bool TryDecodeDUP_ASISDONE_ONLY(const InstData &data, Instruction &inst);

// DUP  <Vd>.<T>, <Vn>.<Ts>[<index>]
bool TryDecodeDUP_ASIMDINS_DV_V(const InstData &data, Instruction &inst);

// STLRH  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLRH_SL32_LDSTEXCL(const InstData &data, Instruction &inst);

// LDUMAXA  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAXA_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMAXAL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAXAL_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMAX  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAX_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMAXL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDUMAXL_32_MEMOP(const InstData &data, Instruction &inst);

// LDUMAXA  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDUMAXA_64_MEMOP(const InstData &data, Instruction &inst);

// LDUMAXAL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDUMAXAL_64_MEMOP(const InstData &data, Instruction &inst);

// LDUMAX  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDUMAX_64_MEMOP(const InstData &data, Instruction &inst);

// LDUMAXL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDUMAXL_64_MEMOP(const InstData &data, Instruction &inst);

// SQNEG  <V><d>, <V><n>
bool TryDecodeSQNEG_ASISDMISC_R(const InstData &data, Instruction &inst);

// SQNEG  <Vd>.<T>, <Vn>.<T>
bool TryDecodeSQNEG_ASIMDMISC_R(const InstData &data, Instruction &inst);

// UHADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUHADD_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// CMP  <Wn|WSP>, #<imm>{, <shift>}
bool TryDecodeCMP_SUBS_32S_ADDSUB_IMM(const InstData &data, Instruction &inst);

// CMP  <Xn|SP>, #<imm>{, <shift>}
bool TryDecodeCMP_SUBS_64S_ADDSUB_IMM(const InstData &data, Instruction &inst);

// CASAH  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCASAH_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASALH  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCASALH_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASH  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCASH_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASLH  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCASLH_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// ADCS  <Wd>, <Wn>, <Wm>
bool TryDecodeADCS_32_ADDSUB_CARRY(const InstData &data, Instruction &inst);

// ADCS  <Xd>, <Xn>, <Xm>
bool TryDecodeADCS_64_ADDSUB_CARRY(const InstData &data, Instruction &inst);

// FRINTZ  <Hd>, <Hn>
bool TryDecodeFRINTZ_H_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTZ  <Sd>, <Sn>
bool TryDecodeFRINTZ_S_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTZ  <Dd>, <Dn>
bool TryDecodeFRINTZ_D_FLOATDP1(const InstData &data, Instruction &inst);

// SCVTF  <Hd>, <Wn>, #<fbits>
bool TryDecodeSCVTF_H32_FLOAT2FIX(const InstData &data, Instruction &inst);

// SCVTF  <Sd>, <Wn>, #<fbits>
bool TryDecodeSCVTF_S32_FLOAT2FIX(const InstData &data, Instruction &inst);

// SCVTF  <Dd>, <Wn>, #<fbits>
bool TryDecodeSCVTF_D32_FLOAT2FIX(const InstData &data, Instruction &inst);

// SCVTF  <Hd>, <Xn>, #<fbits>
bool TryDecodeSCVTF_H64_FLOAT2FIX(const InstData &data, Instruction &inst);

// SCVTF  <Sd>, <Xn>, #<fbits>
bool TryDecodeSCVTF_S64_FLOAT2FIX(const InstData &data, Instruction &inst);

// SCVTF  <Dd>, <Xn>, #<fbits>
bool TryDecodeSCVTF_D64_FLOAT2FIX(const InstData &data, Instruction &inst);

// CSETM  <Wd>, <cond>
bool TryDecodeCSETM_CSINV_32_CONDSEL(const InstData &data, Instruction &inst);

// CSETM  <Xd>, <cond>
bool TryDecodeCSETM_CSINV_64_CONDSEL(const InstData &data, Instruction &inst);

// SQDMLAL  <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
bool TryDecodeSQDMLAL_ASISDELEM_L(const InstData &data, Instruction &inst);

// SQDMLAL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
bool TryDecodeSQDMLAL_ASIMDELEM_L(const InstData &data, Instruction &inst);

// SHL  <V><d>, <V><n>, #<shift>
bool TryDecodeSHL_ASISDSHF_R(const InstData &data, Instruction &inst);

// SHL  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeSHL_ASIMDSHF_R(const InstData &data, Instruction &inst);

// LD2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]
bool TryDecodeLD2_ASISDLSE_R2(const InstData &data, Instruction &inst);

// LD2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeLD2_ASISDLSEP_I2_I(const InstData &data, Instruction &inst);

// LD2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeLD2_ASISDLSEP_R2_R(const InstData &data, Instruction &inst);

// SBFM  <Wd>, <Wn>, #<immr>, #<imms>
bool TryDecodeSBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// SBFM  <Xd>, <Xn>, #<immr>, #<imms>
bool TryDecodeSBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// FMAXV  <V><d>, <Vn>.<T>
bool TryDecodeFMAXV_ASIMDALL_ONLY_H(const InstData &data, Instruction &inst);

// FMAXV  <V><d>, <Vn>.<T>
bool TryDecodeFMAXV_ASIMDALL_ONLY_SD(const InstData &data, Instruction &inst);

// STADDB  <Ws>, [<Xn|SP>]
bool TryDecodeSTADDB_32S_MEMOP(const InstData &data, Instruction &inst);

// STADDLB  <Ws>, [<Xn|SP>]
bool TryDecodeSTADDLB_32S_MEMOP(const InstData &data, Instruction &inst);

// STUMAX  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMAX_32S_MEMOP(const InstData &data, Instruction &inst);

// STUMAXL  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMAXL_32S_MEMOP(const InstData &data, Instruction &inst);

// STUMAX  <Xs>, [<Xn|SP>]
bool TryDecodeSTUMAX_64S_MEMOP(const InstData &data, Instruction &inst);

// STUMAXL  <Xs>, [<Xn|SP>]
bool TryDecodeSTUMAXL_64S_MEMOP(const InstData &data, Instruction &inst);

// SQDMULH  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
bool TryDecodeSQDMULH_ASISDELEM_R(const InstData &data, Instruction &inst);

// SQDMULH  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
bool TryDecodeSQDMULH_ASIMDELEM_R(const InstData &data, Instruction &inst);

// FRSQRTE  <Hd>, <Hn>
bool TryDecodeFRSQRTE_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FRSQRTE  <V><d>, <V><n>
bool TryDecodeFRSQRTE_ASISDMISC_R(const InstData &data, Instruction &inst);

// FRSQRTE  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRSQRTE_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FRSQRTE  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRSQRTE_ASIMDMISC_R(const InstData &data, Instruction &inst);

// ADD  <V><d>, <V><n>, <V><m>
bool TryDecodeADD_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// ADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeADD_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SABDL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeSABDL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// ROR  <Wd>, <Wn>, <Wm>
bool TryDecodeROR_RORV_32_DP_2SRC(const InstData &data, Instruction &inst);

// ROR  <Xd>, <Xn>, <Xm>
bool TryDecodeROR_RORV_64_DP_2SRC(const InstData &data, Instruction &inst);

// UCVTF  <Hd>, <Wn>
bool TryDecodeUCVTF_H32_FLOAT2INT(const InstData &data, Instruction &inst);

// UCVTF  <Sd>, <Wn>
bool TryDecodeUCVTF_S32_FLOAT2INT(const InstData &data, Instruction &inst);

// UCVTF  <Dd>, <Wn>
bool TryDecodeUCVTF_D32_FLOAT2INT(const InstData &data, Instruction &inst);

// UCVTF  <Hd>, <Xn>
bool TryDecodeUCVTF_H64_FLOAT2INT(const InstData &data, Instruction &inst);

// UCVTF  <Sd>, <Xn>
bool TryDecodeUCVTF_S64_FLOAT2INT(const InstData &data, Instruction &inst);

// UCVTF  <Dd>, <Xn>
bool TryDecodeUCVTF_D64_FLOAT2INT(const InstData &data, Instruction &inst);

// UCVTF  <Hd>, <Wn>, #<fbits>
bool TryDecodeUCVTF_H32_FLOAT2FIX(const InstData &data, Instruction &inst);

// UCVTF  <Sd>, <Wn>, #<fbits>
bool TryDecodeUCVTF_S32_FLOAT2FIX(const InstData &data, Instruction &inst);

// UCVTF  <Dd>, <Wn>, #<fbits>
bool TryDecodeUCVTF_D32_FLOAT2FIX(const InstData &data, Instruction &inst);

// UCVTF  <Hd>, <Xn>, #<fbits>
bool TryDecodeUCVTF_H64_FLOAT2FIX(const InstData &data, Instruction &inst);

// UCVTF  <Sd>, <Xn>, #<fbits>
bool TryDecodeUCVTF_S64_FLOAT2FIX(const InstData &data, Instruction &inst);

// UCVTF  <Dd>, <Xn>, #<fbits>
bool TryDecodeUCVTF_D64_FLOAT2FIX(const InstData &data, Instruction &inst);

// MOVI  <Vd>.<T>, #<imm8>{, LSL #0}
bool TryDecodeMOVI_ASIMDIMM_N_B(const InstData &data, Instruction &inst);

// MOVI  <Vd>.<T>, #<imm8>{, LSL #<amount>}
bool TryDecodeMOVI_ASIMDIMM_L_HL(const InstData &data, Instruction &inst);

// MOVI  <Vd>.<T>, #<imm8>{, LSL #<amount>}
bool TryDecodeMOVI_ASIMDIMM_L_SL(const InstData &data, Instruction &inst);

// MOVI  <Vd>.<T>, #<imm8>, MSL #<amount>
bool TryDecodeMOVI_ASIMDIMM_M_SM(const InstData &data, Instruction &inst);

// MOVI  <Dd>, #<imm>
bool TryDecodeMOVI_ASIMDIMM_D_DS(const InstData &data, Instruction &inst);

// MOVI  <Vd>.2D, #<imm>
bool TryDecodeMOVI_ASIMDIMM_D2_D(const InstData &data, Instruction &inst);

// REV16  <Wd>, <Wn>
bool TryDecodeREV16_32_DP_1SRC(const InstData &data, Instruction &inst);

// REV16  <Xd>, <Xn>
bool TryDecodeREV16_64_DP_1SRC(const InstData &data, Instruction &inst);

// SQRDMLAH  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
bool TryDecodeSQRDMLAH_ASISDELEM_R(const InstData &data, Instruction &inst);

// SQRDMLAH  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
bool TryDecodeSQRDMLAH_ASIMDELEM_R(const InstData &data, Instruction &inst);

// FMAXP  <V><d>, <Vn>.<T>
bool TryDecodeFMAXP_ASISDPAIR_ONLY_H(const InstData &data, Instruction &inst);

// FMAXP  <V><d>, <Vn>.<T>
bool TryDecodeFMAXP_ASISDPAIR_ONLY_SD(const InstData &data, Instruction &inst);

// BIF  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeBIF_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FCMLE  <Hd>, <Hn>, #0.0
bool TryDecodeFCMLE_ASISDMISCFP16_FZ(const InstData &data, Instruction &inst);

// FCMLE  <V><d>, <V><n>, #0.0
bool TryDecodeFCMLE_ASISDMISC_FZ(const InstData &data, Instruction &inst);

// FCMLE  <Vd>.<T>, <Vn>.<T>, #0.0
bool TryDecodeFCMLE_ASIMDMISCFP16_FZ(const InstData &data, Instruction &inst);

// FCMLE  <Vd>.<T>, <Vn>.<T>, #0.0
bool TryDecodeFCMLE_ASIMDMISC_FZ(const InstData &data, Instruction &inst);

// DRPS
bool TryDecodeDRPS_64E_BRANCH_REG(const InstData &data, Instruction &inst);

// SLI  <V><d>, <V><n>, #<shift>
bool TryDecodeSLI_ASISDSHF_R(const InstData &data, Instruction &inst);

// SLI  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeSLI_ASIMDSHF_R(const InstData &data, Instruction &inst);

// LDAXRH  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDAXRH_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// BFI  <Wd>, <Wn>, #<lsb>, #<width>
bool TryDecodeBFI_BFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// BFI  <Xd>, <Xn>, #<lsb>, #<width>
bool TryDecodeBFI_BFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// LDADDAB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADDAB_32_MEMOP(const InstData &data, Instruction &inst);

// LDADDALB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADDALB_32_MEMOP(const InstData &data, Instruction &inst);

// LDADDB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADDB_32_MEMOP(const InstData &data, Instruction &inst);

// LDADDLB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDADDLB_32_MEMOP(const InstData &data, Instruction &inst);

// LDRH  <Wt>, [<Xn|SP>], #<simm>
bool TryDecodeLDRH_32_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDRH  <Wt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDRH_32_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDRH  <Wt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDRH_32_LDST_POS(const InstData &data, Instruction &inst);

// SXTB  <Wd>, <Wn>
bool TryDecodeSXTB_SBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// SXTB  <Xd>, <Wn>
bool TryDecodeSXTB_SBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// ERET
bool TryDecodeERET_64E_BRANCH_REG(const InstData &data, Instruction &inst);

// STUMIN  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMIN_32S_MEMOP(const InstData &data, Instruction &inst);

// STUMINL  <Ws>, [<Xn|SP>]
bool TryDecodeSTUMINL_32S_MEMOP(const InstData &data, Instruction &inst);

// STUMIN  <Xs>, [<Xn|SP>]
bool TryDecodeSTUMIN_64S_MEMOP(const InstData &data, Instruction &inst);

// STUMINL  <Xs>, [<Xn|SP>]
bool TryDecodeSTUMINL_64S_MEMOP(const InstData &data, Instruction &inst);

// SHA1SU1  <Vd>.4S, <Vn>.4S
bool TryDecodeSHA1SU1_VV_CRYPTOSHA2(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T> }, [<Xn|SP>]
bool TryDecodeLD1_ASISDLSE_R1_1V(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]
bool TryDecodeLD1_ASISDLSE_R2_2V(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]
bool TryDecodeLD1_ASISDLSE_R3_3V(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]
bool TryDecodeLD1_ASISDLSE_R4_4V(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeLD1_ASISDLSEP_I1_I1(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeLD1_ASISDLSEP_R1_R1(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeLD1_ASISDLSEP_I2_I2(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeLD1_ASISDLSEP_R2_R2(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeLD1_ASISDLSEP_I3_I3(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeLD1_ASISDLSEP_R3_R3(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeLD1_ASISDLSEP_I4_I4(const InstData &data, Instruction &inst);

// LD1  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeLD1_ASISDLSEP_R4_R4(const InstData &data, Instruction &inst);

// SHA1H  <Sd>, <Sn>
bool TryDecodeSHA1H_SS_CRYPTOSHA2(const InstData &data, Instruction &inst);

// FRINTM  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTM_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FRINTM  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTM_ASIMDMISC_R(const InstData &data, Instruction &inst);

// STURH  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTURH_32_LDST_UNSCALED(const InstData &data, Instruction &inst);

// SQSHLU  <V><d>, <V><n>, #<shift>
bool TryDecodeSQSHLU_ASISDSHF_R(const InstData &data, Instruction &inst);

// SQSHLU  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeSQSHLU_ASIMDSHF_R(const InstData &data, Instruction &inst);

// UMULL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
bool TryDecodeUMULL_ASIMDELEM_L(const InstData &data, Instruction &inst);

// NOT  <Vd>.<T>, <Vn>.<T>
bool TryDecodeNOT_ASIMDMISC_R(const InstData &data, Instruction &inst);

// LDR  <Bt>, [<Xn|SP>], #<simm>
bool TryDecodeLDR_B_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDR  <Ht>, [<Xn|SP>], #<simm>
bool TryDecodeLDR_H_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDR  <St>, [<Xn|SP>], #<simm>
bool TryDecodeLDR_S_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDR  <Dt>, [<Xn|SP>], #<simm>
bool TryDecodeLDR_D_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDR  <Qt>, [<Xn|SP>], #<simm>
bool TryDecodeLDR_Q_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDR  <Bt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDR_B_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDR  <Ht>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDR_H_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDR  <St>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDR_S_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDR  <Dt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDR_D_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDR  <Qt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDR_Q_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDR  <Bt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDR_B_LDST_POS(const InstData &data, Instruction &inst);

// LDR  <Ht>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDR_H_LDST_POS(const InstData &data, Instruction &inst);

// LDR  <St>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDR_S_LDST_POS(const InstData &data, Instruction &inst);

// LDR  <Dt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDR_D_LDST_POS(const InstData &data, Instruction &inst);

// LDR  <Qt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDR_Q_LDST_POS(const InstData &data, Instruction &inst);

// SWPAB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWPAB_32_MEMOP(const InstData &data, Instruction &inst);

// SWPALB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWPALB_32_MEMOP(const InstData &data, Instruction &inst);

// SWPB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWPB_32_MEMOP(const InstData &data, Instruction &inst);

// SWPLB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeSWPLB_32_MEMOP(const InstData &data, Instruction &inst);

// FMOV  <Vd>.<T>, #<imm>
bool TryDecodeFMOV_ASIMDIMM_H_H(const InstData &data, Instruction &inst);

// FMOV  <Vd>.<T>, #<imm>
bool TryDecodeFMOV_ASIMDIMM_S_S(const InstData &data, Instruction &inst);

// FMOV  <Vd>.2D, #<imm>
bool TryDecodeFMOV_ASIMDIMM_D2_D(const InstData &data, Instruction &inst);

// FMIN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMIN_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FMIN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMIN_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SQXTUN  <Vb><d>, <Va><n>
bool TryDecodeSQXTUN_ASISDMISC_N(const InstData &data, Instruction &inst);

// SQXTUN{2}  <Vd>.<Tb>, <Vn>.<Ta>
bool TryDecodeSQXTUN_ASIMDMISC_N(const InstData &data, Instruction &inst);

// LDEORAB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEORAB_32_MEMOP(const InstData &data, Instruction &inst);

// LDEORALB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEORALB_32_MEMOP(const InstData &data, Instruction &inst);

// LDEORB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEORB_32_MEMOP(const InstData &data, Instruction &inst);

// LDEORLB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDEORLB_32_MEMOP(const InstData &data, Instruction &inst);

// FCVTPS  <Hd>, <Hn>
bool TryDecodeFCVTPS_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTPS  <V><d>, <V><n>
bool TryDecodeFCVTPS_ASISDMISC_R(const InstData &data, Instruction &inst);

// FCVTPS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTPS_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTPS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTPS_ASIMDMISC_R(const InstData &data, Instruction &inst);

// LDR  <St>, <label>
bool TryDecodeLDR_S_LOADLIT(const InstData &data, Instruction &inst);

// LDR  <Dt>, <label>
bool TryDecodeLDR_D_LOADLIT(const InstData &data, Instruction &inst);

// LDR  <Qt>, <label>
bool TryDecodeLDR_Q_LOADLIT(const InstData &data, Instruction &inst);

// FRINTP  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTP_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FRINTP  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTP_ASIMDMISC_R(const InstData &data, Instruction &inst);

// LDLARB  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDLARB_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// FNEG  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFNEG_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FNEG  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFNEG_ASIMDMISC_R(const InstData &data, Instruction &inst);

// ADDHN{2}  <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>
bool TryDecodeADDHN_ASIMDDIFF_N(const InstData &data, Instruction &inst);

// LDNP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeLDNP_32_LDSTNAPAIR_OFFS(const InstData &data, Instruction &inst);

// LDNP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeLDNP_64_LDSTNAPAIR_OFFS(const InstData &data, Instruction &inst);

// SQRSHRN  <Vb><d>, <Va><n>, #<shift>
bool TryDecodeSQRSHRN_ASISDSHF_N(const InstData &data, Instruction &inst);

// SQRSHRN{2}  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
bool TryDecodeSQRSHRN_ASIMDSHF_N(const InstData &data, Instruction &inst);

// CMGT  <V><d>, <V><n>, <V><m>
bool TryDecodeCMGT_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// CMGT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeCMGT_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// ST4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]
bool TryDecodeST4_ASISDLSE_R4(const InstData &data, Instruction &inst);

// ST4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeST4_ASISDLSEP_I4_I(const InstData &data, Instruction &inst);

// ST4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeST4_ASISDLSEP_R4_R(const InstData &data, Instruction &inst);

// ASRV  <Wd>, <Wn>, <Wm>
bool TryDecodeASRV_32_DP_2SRC(const InstData &data, Instruction &inst);

// ASRV  <Xd>, <Xn>, <Xm>
bool TryDecodeASRV_64_DP_2SRC(const InstData &data, Instruction &inst);

// UHSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUHSUB_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// CMHS  <V><d>, <V><n>, <V><m>
bool TryDecodeCMHS_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// CMHS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeCMHS_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// MOVZ  <Wd>, #<imm>{, LSL #<shift>}
bool TryDecodeMOVZ_32_MOVEWIDE(const InstData &data, Instruction &inst);

// MOVZ  <Xd>, #<imm>{, LSL #<shift>}
bool TryDecodeMOVZ_64_MOVEWIDE(const InstData &data, Instruction &inst);

// SADDW{2}  <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>
bool TryDecodeSADDW_ASIMDDIFF_W(const InstData &data, Instruction &inst);

// SADDLP  <Vd>.<Ta>, <Vn>.<Tb>
bool TryDecodeSADDLP_ASIMDMISC_P(const InstData &data, Instruction &inst);

// UMNEGL  <Xd>, <Wn>, <Wm>
bool TryDecodeUMNEGL_UMSUBL_64WA_DP_3SRC(const InstData &data,
                                         Instruction &inst);

// ST2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]
bool TryDecodeST2_ASISDLSE_R2(const InstData &data, Instruction &inst);

// ST2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeST2_ASISDLSEP_I2_I(const InstData &data, Instruction &inst);

// ST2  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeST2_ASISDLSEP_R2_R(const InstData &data, Instruction &inst);

// UXTL{2}  <Vd>.<Ta>, <Vn>.<Tb>
bool TryDecodeUXTL_USHLL_ASIMDSHF_L(const InstData &data, Instruction &inst);

// LDSMINA  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMINA_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMINAL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMINAL_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMIN  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMIN_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMINL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMINL_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMINA  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSMINA_64_MEMOP(const InstData &data, Instruction &inst);

// LDSMINAL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSMINAL_64_MEMOP(const InstData &data, Instruction &inst);

// LDSMIN  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSMIN_64_MEMOP(const InstData &data, Instruction &inst);

// LDSMINL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSMINL_64_MEMOP(const InstData &data, Instruction &inst);

// PSB CSYNC
bool TryDecodePSB_HC_SYSTEM(const InstData &data, Instruction &inst);

// FMUL  <Hd>, <Hn>, <Vm>.H[<index>]
bool TryDecodeFMUL_ASISDELEM_RH_H(const InstData &data, Instruction &inst);

// FMUL  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
bool TryDecodeFMUL_ASISDELEM_R_SD(const InstData &data, Instruction &inst);

// FMUL  <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>]
bool TryDecodeFMUL_ASIMDELEM_RH_H(const InstData &data, Instruction &inst);

// FMUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
bool TryDecodeFMUL_ASIMDELEM_R_SD(const InstData &data, Instruction &inst);

// SHADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSHADD_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FMINP  <V><d>, <Vn>.<T>
bool TryDecodeFMINP_ASISDPAIR_ONLY_H(const InstData &data, Instruction &inst);

// FMINP  <V><d>, <Vn>.<T>
bool TryDecodeFMINP_ASISDPAIR_ONLY_SD(const InstData &data, Instruction &inst);

// REV64  <Vd>.<T>, <Vn>.<T>
bool TryDecodeREV64_ASIMDMISC_R(const InstData &data, Instruction &inst);

// SSUBW{2}  <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>
bool TryDecodeSSUBW_ASIMDDIFF_W(const InstData &data, Instruction &inst);

// MOV  <Wd>, <Vn>.S[<index>]
bool TryDecodeMOV_UMOV_ASIMDINS_W_W(const InstData &data, Instruction &inst);

// MOV  <Xd>, <Vn>.D[<index>]
bool TryDecodeMOV_UMOV_ASIMDINS_X_X(const InstData &data, Instruction &inst);

// MLS  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
bool TryDecodeMLS_ASIMDELEM_R(const InstData &data, Instruction &inst);

// SQDMLSL  <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
bool TryDecodeSQDMLSL_ASISDELEM_L(const InstData &data, Instruction &inst);

// SQDMLSL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
bool TryDecodeSQDMLSL_ASIMDELEM_L(const InstData &data, Instruction &inst);

// CINC  <Wd>, <Wn>, <cond>
bool TryDecodeCINC_CSINC_32_CONDSEL(const InstData &data, Instruction &inst);

// CINC  <Xd>, <Xn>, <cond>
bool TryDecodeCINC_CSINC_64_CONDSEL(const InstData &data, Instruction &inst);

// CSINV  <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSINV_32_CONDSEL(const InstData &data, Instruction &inst);

// CSINV  <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSINV_64_CONDSEL(const InstData &data, Instruction &inst);

// FCVTZU  <V><d>, <V><n>, #<fbits>
bool TryDecodeFCVTZU_ASISDSHF_C(const InstData &data, Instruction &inst);

// FCVTZU  <Vd>.<T>, <Vn>.<T>, #<fbits>
bool TryDecodeFCVTZU_ASIMDSHF_C(const InstData &data, Instruction &inst);

// SSHL  <V><d>, <V><n>, <V><m>
bool TryDecodeSSHL_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// SSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSSHL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// UXTB  <Wd>, <Wn>
bool TryDecodeUXTB_UBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// SSRA  <V><d>, <V><n>, #<shift>
bool TryDecodeSSRA_ASISDSHF_R(const InstData &data, Instruction &inst);

// SSRA  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeSSRA_ASIMDSHF_R(const InstData &data, Instruction &inst);

// LDRSW  <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeLDRSW_64_LDST_REGOFF(const InstData &data, Instruction &inst);

// SQSHL  <V><d>, <V><n>, <V><m>
bool TryDecodeSQSHL_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// SQSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSQSHL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// ADDV  <V><d>, <Vn>.<T>
bool TryDecodeADDV_ASIMDALL_ONLY(const InstData &data, Instruction &inst);

// PMUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodePMUL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SMLSL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
bool TryDecodeSMLSL_ASIMDELEM_L(const InstData &data, Instruction &inst);

// NEG  <Wd>, <Wm>{, <shift> #<amount>}
bool TryDecodeNEG_SUB_32_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// NEG  <Xd>, <Xm>{, <shift> #<amount>}
bool TryDecodeNEG_SUB_64_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// FCMP  <Hn>, <Hm>
bool TryDecodeFCMP_H_FLOATCMP(const InstData &data, Instruction &inst);

// FCMP  <Hn>, #0.0
bool TryDecodeFCMP_HZ_FLOATCMP(const InstData &data, Instruction &inst);

// FCMP  <Sn>, <Sm>
bool TryDecodeFCMP_S_FLOATCMP(const InstData &data, Instruction &inst);

// FCMP  <Sn>, #0.0
bool TryDecodeFCMP_SZ_FLOATCMP(const InstData &data, Instruction &inst);

// FCMP  <Dn>, <Dm>
bool TryDecodeFCMP_D_FLOATCMP(const InstData &data, Instruction &inst);

// FCMP  <Dn>, #0.0
bool TryDecodeFCMP_DZ_FLOATCMP(const InstData &data, Instruction &inst);

// ORR  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeORR_32_LOG_SHIFT(const InstData &data, Instruction &inst);

// ORR  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeORR_64_LOG_SHIFT(const InstData &data, Instruction &inst);

// SHA1SU0  <Vd>.4S, <Vn>.4S, <Vm>.4S
bool TryDecodeSHA1SU0_VVV_CRYPTOSHA3(const InstData &data, Instruction &inst);

// STSET  <Ws>, [<Xn|SP>]
bool TryDecodeSTSET_32S_MEMOP(const InstData &data, Instruction &inst);

// STSETL  <Ws>, [<Xn|SP>]
bool TryDecodeSTSETL_32S_MEMOP(const InstData &data, Instruction &inst);

// STSET  <Xs>, [<Xn|SP>]
bool TryDecodeSTSET_64S_MEMOP(const InstData &data, Instruction &inst);

// STSETL  <Xs>, [<Xn|SP>]
bool TryDecodeSTSETL_64S_MEMOP(const InstData &data, Instruction &inst);

// MLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeMLA_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// ADDS  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeADDS_32_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// ADDS  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeADDS_64_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// LD3R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]
bool TryDecodeLD3R_ASISDLSO_R3(const InstData &data, Instruction &inst);

// LD3R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeLD3R_ASISDLSOP_R3_I(const InstData &data, Instruction &inst);

// LD3R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeLD3R_ASISDLSOP_RX3_R(const InstData &data, Instruction &inst);

// PRFM  (<prfop>|#<imm5>), <label>
bool TryDecodePRFM_P_LOADLIT(const InstData &data, Instruction &inst);

// CASAB  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCASAB_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASALB  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCASALB_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASB  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCASB_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// CASLB  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeCASLB_C32_LDSTEXCL(const InstData &data, Instruction &inst);

// NEGS  <Wd>, <Wm>{, <shift> #<amount>}
bool TryDecodeNEGS_SUBS_32_ADDSUB_SHIFT(const InstData &data,
                                        Instruction &inst);

// NEGS  <Xd>, <Xm>{, <shift> #<amount>}
bool TryDecodeNEGS_SUBS_64_ADDSUB_SHIFT(const InstData &data,
                                        Instruction &inst);

// LDSMAXAH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAXAH_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMAXALH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAXALH_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMAXH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAXH_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMAXLH  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAXLH_32_MEMOP(const InstData &data, Instruction &inst);

// MSUB  <Wd>, <Wn>, <Wm>, <Wa>
bool TryDecodeMSUB_32A_DP_3SRC(const InstData &data, Instruction &inst);

// MSUB  <Xd>, <Xn>, <Xm>, <Xa>
bool TryDecodeMSUB_64A_DP_3SRC(const InstData &data, Instruction &inst);

// LD4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]
bool TryDecodeLD4_ASISDLSE_R4(const InstData &data, Instruction &inst);

// LD4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeLD4_ASISDLSEP_I4_I(const InstData &data, Instruction &inst);

// LD4  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeLD4_ASISDLSEP_R4_R(const InstData &data, Instruction &inst);

// UQXTN  <Vb><d>, <Va><n>
bool TryDecodeUQXTN_ASISDMISC_N(const InstData &data, Instruction &inst);

// UQXTN{2}  <Vd>.<Tb>, <Vn>.<Ta>
bool TryDecodeUQXTN_ASIMDMISC_N(const InstData &data, Instruction &inst);

// TBZ  <R><t>, #<imm>, <label>
bool TryDecodeTBZ_ONLY_TESTBRANCH(const InstData &data, Instruction &inst);

// FMINNMV  <V><d>, <Vn>.<T>
bool TryDecodeFMINNMV_ASIMDALL_ONLY_H(const InstData &data, Instruction &inst);

// FMINNMV  <V><d>, <Vn>.<T>
bool TryDecodeFMINNMV_ASIMDALL_ONLY_SD(const InstData &data, Instruction &inst);

// FCVTZS  <Hd>, <Hn>
bool TryDecodeFCVTZS_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTZS  <V><d>, <V><n>
bool TryDecodeFCVTZS_ASISDMISC_R(const InstData &data, Instruction &inst);

// FCVTZS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTZS_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTZS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTZS_ASIMDMISC_R(const InstData &data, Instruction &inst);

// FMAXNM  <Hd>, <Hn>, <Hm>
bool TryDecodeFMAXNM_H_FLOATDP2(const InstData &data, Instruction &inst);

// FMAXNM  <Sd>, <Sn>, <Sm>
bool TryDecodeFMAXNM_S_FLOATDP2(const InstData &data, Instruction &inst);

// FMAXNM  <Dd>, <Dn>, <Dm>
bool TryDecodeFMAXNM_D_FLOATDP2(const InstData &data, Instruction &inst);

// LDR  <Wt>, [<Xn|SP>], #<simm>
bool TryDecodeLDR_32_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDR  <Xt>, [<Xn|SP>], #<simm>
bool TryDecodeLDR_64_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDR  <Wt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDR_32_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDR  <Xt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDR_64_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDR  <Wt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDR_32_LDST_POS(const InstData &data, Instruction &inst);

// LDR  <Xt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDR_64_LDST_POS(const InstData &data, Instruction &inst);

// CNT  <Vd>.<T>, <Vn>.<T>
bool TryDecodeCNT_ASIMDMISC_R(const InstData &data, Instruction &inst);

// SQSHL  <V><d>, <V><n>, #<shift>
bool TryDecodeSQSHL_ASISDSHF_R(const InstData &data, Instruction &inst);

// SQSHL  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeSQSHL_ASIMDSHF_R(const InstData &data, Instruction &inst);

// LDTR  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDTR_32_LDST_UNPRIV(const InstData &data, Instruction &inst);

// LDTR  <Xt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDTR_64_LDST_UNPRIV(const InstData &data, Instruction &inst);

// CCMP  <Wn>, #<imm>, #<nzcv>, <cond>
bool TryDecodeCCMP_32_CONDCMP_IMM(const InstData &data, Instruction &inst);

// CCMP  <Xn>, #<imm>, #<nzcv>, <cond>
bool TryDecodeCCMP_64_CONDCMP_IMM(const InstData &data, Instruction &inst);

// UZP2  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUZP2_ASIMDPERM_ONLY(const InstData &data, Instruction &inst);

// LDURB  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDURB_32_LDST_UNSCALED(const InstData &data, Instruction &inst);

// SQRDMLSH  <V><d>, <V><n>, <V><m>
bool TryDecodeSQRDMLSH_ASISDSAME2_ONLY(const InstData &data, Instruction &inst);

// SQRDMLSH  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSQRDMLSH_ASIMDSAME2_ONLY(const InstData &data, Instruction &inst);

// MOV  <Vd>.<Ts>[<index>], <R><n>
bool TryDecodeMOV_INS_ASIMDINS_IR_R(const InstData &data, Instruction &inst);

// LDTRSB  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDTRSB_32_LDST_UNPRIV(const InstData &data, Instruction &inst);

// LDTRSB  <Xt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDTRSB_64_LDST_UNPRIV(const InstData &data, Instruction &inst);

// SMINV  <V><d>, <Vn>.<T>
bool TryDecodeSMINV_ASIMDALL_ONLY(const InstData &data, Instruction &inst);

// URHADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeURHADD_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// AND  <Wd|WSP>, <Wn>, #<imm>
bool TryDecodeAND_32_LOG_IMM(const InstData &data, Instruction &inst);

// AND  <Xd|SP>, <Xn>, #<imm>
bool TryDecodeAND_64_LOG_IMM(const InstData &data, Instruction &inst);

// SABD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSABD_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FCMGE  <Hd>, <Hn>, <Hm>
bool TryDecodeFCMGE_ASISDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FCMGE  <V><d>, <V><n>, <V><m>
bool TryDecodeFCMGE_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// FCMGE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFCMGE_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FCMGE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFCMGE_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// MVN  <Vd>.<T>, <Vn>.<T>
bool TryDecodeMVN_NOT_ASIMDMISC_R(const InstData &data, Instruction &inst);

// STSMIN  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMIN_32S_MEMOP(const InstData &data, Instruction &inst);

// STSMINL  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMINL_32S_MEMOP(const InstData &data, Instruction &inst);

// STSMIN  <Xs>, [<Xn|SP>]
bool TryDecodeSTSMIN_64S_MEMOP(const InstData &data, Instruction &inst);

// STSMINL  <Xs>, [<Xn|SP>]
bool TryDecodeSTSMINL_64S_MEMOP(const InstData &data, Instruction &inst);

// TRN1  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeTRN1_ASIMDPERM_ONLY(const InstData &data, Instruction &inst);

// SBCS  <Wd>, <Wn>, <Wm>
bool TryDecodeSBCS_32_ADDSUB_CARRY(const InstData &data, Instruction &inst);

// SBCS  <Xd>, <Xn>, <Xm>
bool TryDecodeSBCS_64_ADDSUB_CARRY(const InstData &data, Instruction &inst);

// SMULL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeSMULL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// LSRV  <Wd>, <Wn>, <Wm>
bool TryDecodeLSRV_32_DP_2SRC(const InstData &data, Instruction &inst);

// LSRV  <Xd>, <Xn>, <Xm>
bool TryDecodeLSRV_64_DP_2SRC(const InstData &data, Instruction &inst);

// URSQRTE  <Vd>.<T>, <Vn>.<T>
bool TryDecodeURSQRTE_ASIMDMISC_R(const InstData &data, Instruction &inst);

// FCCMPE  <Hn>, <Hm>, #<nzcv>, <cond>
bool TryDecodeFCCMPE_H_FLOATCCMP(const InstData &data, Instruction &inst);

// FCCMPE  <Sn>, <Sm>, #<nzcv>, <cond>
bool TryDecodeFCCMPE_S_FLOATCCMP(const InstData &data, Instruction &inst);

// FCCMPE  <Dn>, <Dm>, #<nzcv>, <cond>
bool TryDecodeFCCMPE_D_FLOATCCMP(const InstData &data, Instruction &inst);

// FMAXP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMAXP_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FMAXP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMAXP_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// MUL  <Wd>, <Wn>, <Wm>
bool TryDecodeMUL_MADD_32A_DP_3SRC(const InstData &data, Instruction &inst);

// MUL  <Xd>, <Xn>, <Xm>
bool TryDecodeMUL_MADD_64A_DP_3SRC(const InstData &data, Instruction &inst);

// STTR  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTTR_32_LDST_UNPRIV(const InstData &data, Instruction &inst);

// STTR  <Xt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTTR_64_LDST_UNPRIV(const InstData &data, Instruction &inst);

// FCMGT  <Hd>, <Hn>, #0.0
bool TryDecodeFCMGT_ASISDMISCFP16_FZ(const InstData &data, Instruction &inst);

// FCMGT  <V><d>, <V><n>, #0.0
bool TryDecodeFCMGT_ASISDMISC_FZ(const InstData &data, Instruction &inst);

// FCMGT  <Vd>.<T>, <Vn>.<T>, #0.0
bool TryDecodeFCMGT_ASIMDMISCFP16_FZ(const InstData &data, Instruction &inst);

// FCMGT  <Vd>.<T>, <Vn>.<T>, #0.0
bool TryDecodeFCMGT_ASIMDMISC_FZ(const InstData &data, Instruction &inst);

// BSL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeBSL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// UQSUB  <V><d>, <V><n>, <V><m>
bool TryDecodeUQSUB_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// UQSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUQSUB_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// WFI
bool TryDecodeWFI_HI_SYSTEM(const InstData &data, Instruction &inst);

// LDXRH  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDXRH_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// FMAXNMV  <V><d>, <Vn>.<T>
bool TryDecodeFMAXNMV_ASIMDALL_ONLY_H(const InstData &data, Instruction &inst);

// FMAXNMV  <V><d>, <Vn>.<T>
bool TryDecodeFMAXNMV_ASIMDALL_ONLY_SD(const InstData &data, Instruction &inst);

// STLXR  <Ws>, <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLXR_SR32_LDSTEXCL(const InstData &data, Instruction &inst);

// STLXR  <Ws>, <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLXR_SR64_LDSTEXCL(const InstData &data, Instruction &inst);

// STLRB  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLRB_SL32_LDSTEXCL(const InstData &data, Instruction &inst);

// ST3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]
bool TryDecodeST3_ASISDLSE_R3(const InstData &data, Instruction &inst);

// ST3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeST3_ASISDLSEP_I3_I(const InstData &data, Instruction &inst);

// ST3  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeST3_ASISDLSEP_R3_R(const InstData &data, Instruction &inst);

// SQRDMULH  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
bool TryDecodeSQRDMULH_ASISDELEM_R(const InstData &data, Instruction &inst);

// SQRDMULH  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
bool TryDecodeSQRDMULH_ASIMDELEM_R(const InstData &data, Instruction &inst);

// SXTW  <Xd>, <Wn>
bool TryDecodeSXTW_SBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// USHR  <V><d>, <V><n>, #<shift>
bool TryDecodeUSHR_ASISDSHF_R(const InstData &data, Instruction &inst);

// USHR  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeUSHR_ASIMDSHF_R(const InstData &data, Instruction &inst);

// B  <label>
bool TryDecodeB_ONLY_BRANCH_IMM(const InstData &data, Instruction &inst);

// FCMEQ  <Hd>, <Hn>, #0.0
bool TryDecodeFCMEQ_ASISDMISCFP16_FZ(const InstData &data, Instruction &inst);

// FCMEQ  <V><d>, <V><n>, #0.0
bool TryDecodeFCMEQ_ASISDMISC_FZ(const InstData &data, Instruction &inst);

// FCMEQ  <Vd>.<T>, <Vn>.<T>, #0.0
bool TryDecodeFCMEQ_ASIMDMISCFP16_FZ(const InstData &data, Instruction &inst);

// FCMEQ  <Vd>.<T>, <Vn>.<T>, #0.0
bool TryDecodeFCMEQ_ASIMDMISC_FZ(const InstData &data, Instruction &inst);

// FACGE  <Hd>, <Hn>, <Hm>
bool TryDecodeFACGE_ASISDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FACGE  <V><d>, <V><n>, <V><m>
bool TryDecodeFACGE_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// FACGE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFACGE_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FACGE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFACGE_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// CSEL  <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSEL_32_CONDSEL(const InstData &data, Instruction &inst);

// CSEL  <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSEL_64_CONDSEL(const InstData &data, Instruction &inst);

// FCVTAS  <Wd>, <Hn>
bool TryDecodeFCVTAS_32H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTAS  <Xd>, <Hn>
bool TryDecodeFCVTAS_64H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTAS  <Wd>, <Sn>
bool TryDecodeFCVTAS_32S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTAS  <Xd>, <Sn>
bool TryDecodeFCVTAS_64S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTAS  <Wd>, <Dn>
bool TryDecodeFCVTAS_32D_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTAS  <Xd>, <Dn>
bool TryDecodeFCVTAS_64D_FLOAT2INT(const InstData &data, Instruction &inst);

// LDURSH  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDURSH_32_LDST_UNSCALED(const InstData &data, Instruction &inst);

// LDURSH  <Xt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDURSH_64_LDST_UNSCALED(const InstData &data, Instruction &inst);

// LDURSW  <Xt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDURSW_64_LDST_UNSCALED(const InstData &data, Instruction &inst);

// MOVN  <Wd>, #<imm>{, LSL #<shift>}
bool TryDecodeMOVN_32_MOVEWIDE(const InstData &data, Instruction &inst);

// MOVN  <Xd>, #<imm>{, LSL #<shift>}
bool TryDecodeMOVN_64_MOVEWIDE(const InstData &data, Instruction &inst);

// SXTL{2}  <Vd>.<Ta>, <Vn>.<Tb>
bool TryDecodeSXTL_SSHLL_ASIMDSHF_L(const InstData &data, Instruction &inst);

// ST1  { <Vt>.B }[<index>], [<Xn|SP>]
bool TryDecodeST1_ASISDLSO_B1_1B(const InstData &data, Instruction &inst);

// ST1  { <Vt>.H }[<index>], [<Xn|SP>]
bool TryDecodeST1_ASISDLSO_H1_1H(const InstData &data, Instruction &inst);

// ST1  { <Vt>.S }[<index>], [<Xn|SP>]
bool TryDecodeST1_ASISDLSO_S1_1S(const InstData &data, Instruction &inst);

// ST1  { <Vt>.D }[<index>], [<Xn|SP>]
bool TryDecodeST1_ASISDLSO_D1_1D(const InstData &data, Instruction &inst);

// ST1  { <Vt>.B }[<index>], [<Xn|SP>], #1
bool TryDecodeST1_ASISDLSOP_B1_I1B(const InstData &data, Instruction &inst);

// ST1  { <Vt>.B }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST1_ASISDLSOP_BX1_R1B(const InstData &data, Instruction &inst);

// ST1  { <Vt>.H }[<index>], [<Xn|SP>], #2
bool TryDecodeST1_ASISDLSOP_H1_I1H(const InstData &data, Instruction &inst);

// ST1  { <Vt>.H }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST1_ASISDLSOP_HX1_R1H(const InstData &data, Instruction &inst);

// ST1  { <Vt>.S }[<index>], [<Xn|SP>], #4
bool TryDecodeST1_ASISDLSOP_S1_I1S(const InstData &data, Instruction &inst);

// ST1  { <Vt>.S }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST1_ASISDLSOP_SX1_R1S(const InstData &data, Instruction &inst);

// ST1  { <Vt>.D }[<index>], [<Xn|SP>], #8
bool TryDecodeST1_ASISDLSOP_D1_I1D(const InstData &data, Instruction &inst);

// ST1  { <Vt>.D }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST1_ASISDLSOP_DX1_R1D(const InstData &data, Instruction &inst);

// UZP1  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUZP1_ASIMDPERM_ONLY(const InstData &data, Instruction &inst);

// STUR  <Bt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTUR_B_LDST_UNSCALED(const InstData &data, Instruction &inst);

// STUR  <Ht>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTUR_H_LDST_UNSCALED(const InstData &data, Instruction &inst);

// STUR  <St>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTUR_S_LDST_UNSCALED(const InstData &data, Instruction &inst);

// STUR  <Dt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTUR_D_LDST_UNSCALED(const InstData &data, Instruction &inst);

// STUR  <Qt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeSTUR_Q_LDST_UNSCALED(const InstData &data, Instruction &inst);

// MLA  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
bool TryDecodeMLA_ASIMDELEM_R(const InstData &data, Instruction &inst);

// FCVTPU  <Wd>, <Hn>
bool TryDecodeFCVTPU_32H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTPU  <Xd>, <Hn>
bool TryDecodeFCVTPU_64H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTPU  <Wd>, <Sn>
bool TryDecodeFCVTPU_32S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTPU  <Xd>, <Sn>
bool TryDecodeFCVTPU_64S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTPU  <Wd>, <Dn>
bool TryDecodeFCVTPU_32D_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTPU  <Xd>, <Dn>
bool TryDecodeFCVTPU_64D_FLOAT2INT(const InstData &data, Instruction &inst);

// STSETH  <Ws>, [<Xn|SP>]
bool TryDecodeSTSETH_32S_MEMOP(const InstData &data, Instruction &inst);

// STSETLH  <Ws>, [<Xn|SP>]
bool TryDecodeSTSETLH_32S_MEMOP(const InstData &data, Instruction &inst);

// FMINV  <V><d>, <Vn>.<T>
bool TryDecodeFMINV_ASIMDALL_ONLY_H(const InstData &data, Instruction &inst);

// FMINV  <V><d>, <Vn>.<T>
bool TryDecodeFMINV_ASIMDALL_ONLY_SD(const InstData &data, Instruction &inst);

// MOV  <Wd|WSP>, #<imm>
bool TryDecodeMOV_ORR_32_LOG_IMM(const InstData &data, Instruction &inst);

// MOV  <Xd|SP>, #<imm>
bool TryDecodeMOV_ORR_64_LOG_IMM(const InstData &data, Instruction &inst);

// DSB  <option>|#<imm>
bool TryDecodeDSB_BO_SYSTEM(const InstData &data, Instruction &inst);

// FCVTMS  <Wd>, <Hn>
bool TryDecodeFCVTMS_32H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTMS  <Xd>, <Hn>
bool TryDecodeFCVTMS_64H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTMS  <Wd>, <Sn>
bool TryDecodeFCVTMS_32S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTMS  <Xd>, <Sn>
bool TryDecodeFCVTMS_64S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTMS  <Wd>, <Dn>
bool TryDecodeFCVTMS_32D_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTMS  <Xd>, <Dn>
bool TryDecodeFCVTMS_64D_FLOAT2INT(const InstData &data, Instruction &inst);

// STSMINH  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMINH_32S_MEMOP(const InstData &data, Instruction &inst);

// STSMINLH  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMINLH_32S_MEMOP(const InstData &data, Instruction &inst);

// ST4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>]
bool TryDecodeST4_ASISDLSO_B4_4B(const InstData &data, Instruction &inst);

// ST4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>]
bool TryDecodeST4_ASISDLSO_H4_4H(const InstData &data, Instruction &inst);

// ST4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>]
bool TryDecodeST4_ASISDLSO_S4_4S(const InstData &data, Instruction &inst);

// ST4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>]
bool TryDecodeST4_ASISDLSO_D4_4D(const InstData &data, Instruction &inst);

// ST4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4
bool TryDecodeST4_ASISDLSOP_B4_I4B(const InstData &data, Instruction &inst);

// ST4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST4_ASISDLSOP_BX4_R4B(const InstData &data, Instruction &inst);

// ST4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8
bool TryDecodeST4_ASISDLSOP_H4_I4H(const InstData &data, Instruction &inst);

// ST4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST4_ASISDLSOP_HX4_R4H(const InstData &data, Instruction &inst);

// ST4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16
bool TryDecodeST4_ASISDLSOP_S4_I4S(const InstData &data, Instruction &inst);

// ST4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST4_ASISDLSOP_SX4_R4S(const InstData &data, Instruction &inst);

// ST4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32
bool TryDecodeST4_ASISDLSOP_D4_I4D(const InstData &data, Instruction &inst);

// ST4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeST4_ASISDLSOP_DX4_R4D(const InstData &data, Instruction &inst);

// LDNP  <St1>, <St2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeLDNP_S_LDSTNAPAIR_OFFS(const InstData &data, Instruction &inst);

// LDNP  <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeLDNP_D_LDSTNAPAIR_OFFS(const InstData &data, Instruction &inst);

// LDNP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeLDNP_Q_LDSTNAPAIR_OFFS(const InstData &data, Instruction &inst);

// ADDS  <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
bool TryDecodeADDS_32S_ADDSUB_EXT(const InstData &data, Instruction &inst);

// ADDS  <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
bool TryDecodeADDS_64S_ADDSUB_EXT(const InstData &data, Instruction &inst);

// CBZ  <Wt>, <label>
bool TryDecodeCBZ_32_COMPBRANCH(const InstData &data, Instruction &inst);

// CBZ  <Xt>, <label>
bool TryDecodeCBZ_64_COMPBRANCH(const InstData &data, Instruction &inst);

// URSHL  <V><d>, <V><n>, <V><m>
bool TryDecodeURSHL_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// URSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeURSHL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SQRSHRUN  <Vb><d>, <Va><n>, #<shift>
bool TryDecodeSQRSHRUN_ASISDSHF_N(const InstData &data, Instruction &inst);

// SQRSHRUN{2}  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
bool TryDecodeSQRSHRUN_ASIMDSHF_N(const InstData &data, Instruction &inst);

// ROR  <Wd>, <Ws>, #<shift>
bool TryDecodeROR_EXTR_32_EXTRACT(const InstData &data, Instruction &inst);

// ROR  <Xd>, <Xs>, #<shift>
bool TryDecodeROR_EXTR_64_EXTRACT(const InstData &data, Instruction &inst);

// FRINTI  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTI_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FRINTI  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTI_ASIMDMISC_R(const InstData &data, Instruction &inst);

// LDXRB  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDXRB_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// STP  <St1>, <St2>, [<Xn|SP>], #<imm>
bool TryDecodeSTP_S_LDSTPAIR_POST(const InstData &data, Instruction &inst);

// STP  <Dt1>, <Dt2>, [<Xn|SP>], #<imm>
bool TryDecodeSTP_D_LDSTPAIR_POST(const InstData &data, Instruction &inst);

// STP  <Qt1>, <Qt2>, [<Xn|SP>], #<imm>
bool TryDecodeSTP_Q_LDSTPAIR_POST(const InstData &data, Instruction &inst);

// STP  <St1>, <St2>, [<Xn|SP>, #<imm>]!
bool TryDecodeSTP_S_LDSTPAIR_PRE(const InstData &data, Instruction &inst);

// STP  <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!
bool TryDecodeSTP_D_LDSTPAIR_PRE(const InstData &data, Instruction &inst);

// STP  <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!
bool TryDecodeSTP_Q_LDSTPAIR_PRE(const InstData &data, Instruction &inst);

// STP  <St1>, <St2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeSTP_S_LDSTPAIR_OFF(const InstData &data, Instruction &inst);

// STP  <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeSTP_D_LDSTPAIR_OFF(const InstData &data, Instruction &inst);

// STP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeSTP_Q_LDSTPAIR_OFF(const InstData &data, Instruction &inst);

// ADR  <Xd>, <label>
bool TryDecodeADR_ONLY_PCRELADDR(const InstData &data, Instruction &inst);

// LDSMINAB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMINAB_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMINALB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMINALB_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMINB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMINB_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMINLB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMINLB_32_MEMOP(const InstData &data, Instruction &inst);

// UBFIZ  <Wd>, <Wn>, #<lsb>, #<width>
bool TryDecodeUBFIZ_UBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// UBFIZ  <Xd>, <Xn>, #<lsb>, #<width>
bool TryDecodeUBFIZ_UBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// LD4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>]
bool TryDecodeLD4_ASISDLSO_B4_4B(const InstData &data, Instruction &inst);

// LD4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>]
bool TryDecodeLD4_ASISDLSO_H4_4H(const InstData &data, Instruction &inst);

// LD4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>]
bool TryDecodeLD4_ASISDLSO_S4_4S(const InstData &data, Instruction &inst);

// LD4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>]
bool TryDecodeLD4_ASISDLSO_D4_4D(const InstData &data, Instruction &inst);

// LD4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4
bool TryDecodeLD4_ASISDLSOP_B4_I4B(const InstData &data, Instruction &inst);

// LD4  { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD4_ASISDLSOP_BX4_R4B(const InstData &data, Instruction &inst);

// LD4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8
bool TryDecodeLD4_ASISDLSOP_H4_I4H(const InstData &data, Instruction &inst);

// LD4  { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD4_ASISDLSOP_HX4_R4H(const InstData &data, Instruction &inst);

// LD4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16
bool TryDecodeLD4_ASISDLSOP_S4_I4S(const InstData &data, Instruction &inst);

// LD4  { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD4_ASISDLSOP_SX4_R4S(const InstData &data, Instruction &inst);

// LD4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32
bool TryDecodeLD4_ASISDLSOP_D4_I4D(const InstData &data, Instruction &inst);

// LD4  { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD4_ASISDLSOP_DX4_R4D(const InstData &data, Instruction &inst);

// STRB  <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
bool TryDecodeSTRB_32B_LDST_REGOFF(const InstData &data, Instruction &inst);

// STRB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
bool TryDecodeSTRB_32BL_LDST_REGOFF(const InstData &data, Instruction &inst);

// UMAX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUMAX_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// CRC32B  <Wd>, <Wn>, <Wm>
bool TryDecodeCRC32B_32C_DP_2SRC(const InstData &data, Instruction &inst);

// CRC32H  <Wd>, <Wn>, <Wm>
bool TryDecodeCRC32H_32C_DP_2SRC(const InstData &data, Instruction &inst);

// CRC32W  <Wd>, <Wn>, <Wm>
bool TryDecodeCRC32W_32C_DP_2SRC(const InstData &data, Instruction &inst);

// CRC32X  <Wd>, <Wn>, <Xm>
bool TryDecodeCRC32X_64C_DP_2SRC(const InstData &data, Instruction &inst);

// URSHR  <V><d>, <V><n>, #<shift>
bool TryDecodeURSHR_ASISDSHF_R(const InstData &data, Instruction &inst);

// URSHR  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeURSHR_ASIMDSHF_R(const InstData &data, Instruction &inst);

// PRFM  (<prfop>|#<imm5>), [<Xn|SP>{, #<pimm>}]
bool TryDecodePRFM_P_LDST_POS(const InstData &data, Instruction &inst);

// SUBS  <Wd>, <Wn|WSP>, #<imm>{, <shift>}
bool TryDecodeSUBS_32S_ADDSUB_IMM(const InstData &data, Instruction &inst);

// SUBS  <Xd>, <Xn|SP>, #<imm>{, <shift>}
bool TryDecodeSUBS_64S_ADDSUB_IMM(const InstData &data, Instruction &inst);

// SUBS  <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
bool TryDecodeSUBS_32S_ADDSUB_EXT(const InstData &data, Instruction &inst);

// SUBS  <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
bool TryDecodeSUBS_64S_ADDSUB_EXT(const InstData &data, Instruction &inst);

// SYSL  <Xt>, #<op1>, <Cn>, <Cm>, #<op2>
bool TryDecodeSYSL_RC_SYSTEM(const InstData &data, Instruction &inst);

// SMSUBL  <Xd>, <Wn>, <Wm>, <Xa>
bool TryDecodeSMSUBL_64WA_DP_3SRC(const InstData &data, Instruction &inst);

// URSRA  <V><d>, <V><n>, #<shift>
bool TryDecodeURSRA_ASISDSHF_R(const InstData &data, Instruction &inst);

// URSRA  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeURSRA_ASIMDSHF_R(const InstData &data, Instruction &inst);

// LDURH  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDURH_32_LDST_UNSCALED(const InstData &data, Instruction &inst);

// SUB  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeSUB_32_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// SUB  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeSUB_64_ADDSUB_SHIFT(const InstData &data, Instruction &inst);

// SRI  <V><d>, <V><n>, #<shift>
bool TryDecodeSRI_ASISDSHF_R(const InstData &data, Instruction &inst);

// SRI  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeSRI_ASIMDSHF_R(const InstData &data, Instruction &inst);

// UMAXP  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUMAXP_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// IC  <ic_op>{, <Xt>}
bool TryDecodeIC_SYS_CR_SYSTEM(const InstData &data, Instruction &inst);

// LDTRSH  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDTRSH_32_LDST_UNPRIV(const InstData &data, Instruction &inst);

// LDTRSH  <Xt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDTRSH_64_LDST_UNPRIV(const InstData &data, Instruction &inst);

// SADALP  <Vd>.<Ta>, <Vn>.<Tb>
bool TryDecodeSADALP_ASIMDMISC_P(const InstData &data, Instruction &inst);

// LDTRH  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDTRH_32_LDST_UNPRIV(const InstData &data, Instruction &inst);

// SMAX  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSMAX_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FCVTPU  <Hd>, <Hn>
bool TryDecodeFCVTPU_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTPU  <V><d>, <V><n>
bool TryDecodeFCVTPU_ASISDMISC_R(const InstData &data, Instruction &inst);

// FCVTPU  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTPU_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTPU  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTPU_ASIMDMISC_R(const InstData &data, Instruction &inst);

// RET  {<Xn>}
bool TryDecodeRET_64R_BRANCH_REG(const InstData &data, Instruction &inst);

// UQRSHL  <V><d>, <V><n>, <V><m>
bool TryDecodeUQRSHL_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// UQRSHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUQRSHL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// LDRB  <Wt>, [<Xn|SP>], #<simm>
bool TryDecodeLDRB_32_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDRB  <Wt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDRB_32_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDRB  <Wt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDRB_32_LDST_POS(const InstData &data, Instruction &inst);

// FCVTXN  <Vb><d>, <Va><n>
bool TryDecodeFCVTXN_ASISDMISC_N(const InstData &data, Instruction &inst);

// FCVTXN{2}  <Vd>.<Tb>, <Vn>.<Ta>
bool TryDecodeFCVTXN_ASIMDMISC_N(const InstData &data, Instruction &inst);

// MSR  <pstatefield>, #<imm>
bool TryDecodeMSR_SI_SYSTEM(const InstData &data, Instruction &inst);

// UABDL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeUABDL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// MSR  (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>
bool TryDecodeMSR_SR_SYSTEM(const InstData &data, Instruction &inst);

// LDRH  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeLDRH_32_LDST_REGOFF(const InstData &data, Instruction &inst);

// UQSHL  <V><d>, <V><n>, #<shift>
bool TryDecodeUQSHL_ASISDSHF_R(const InstData &data, Instruction &inst);

// UQSHL  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeUQSHL_ASIMDSHF_R(const InstData &data, Instruction &inst);

// FMINNMP  <V><d>, <Vn>.<T>
bool TryDecodeFMINNMP_ASISDPAIR_ONLY_H(const InstData &data, Instruction &inst);

// FMINNMP  <V><d>, <Vn>.<T>
bool TryDecodeFMINNMP_ASISDPAIR_ONLY_SD(const InstData &data,
                                        Instruction &inst);

// UMADDL  <Xd>, <Wn>, <Wm>, <Xa>
bool TryDecodeUMADDL_64WA_DP_3SRC(const InstData &data, Instruction &inst);

// FMOV  <Hd>, <Hn>
bool TryDecodeFMOV_H_FLOATDP1(const InstData &data, Instruction &inst);

// FMOV  <Sd>, <Sn>
bool TryDecodeFMOV_S_FLOATDP1(const InstData &data, Instruction &inst);

// FMOV  <Dd>, <Dn>
bool TryDecodeFMOV_D_FLOATDP1(const InstData &data, Instruction &inst);

// SRHADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSRHADD_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// NGC  <Wd>, <Wm>
bool TryDecodeNGC_SBC_32_ADDSUB_CARRY(const InstData &data, Instruction &inst);

// NGC  <Xd>, <Xm>
bool TryDecodeNGC_SBC_64_ADDSUB_CARRY(const InstData &data, Instruction &inst);

// SBFIZ  <Wd>, <Wn>, #<lsb>, #<width>
bool TryDecodeSBFIZ_SBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// SBFIZ  <Xd>, <Xn>, #<lsb>, #<width>
bool TryDecodeSBFIZ_SBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// UMSUBL  <Xd>, <Wn>, <Wm>, <Xa>
bool TryDecodeUMSUBL_64WA_DP_3SRC(const InstData &data, Instruction &inst);

// FCVTMU  <Wd>, <Hn>
bool TryDecodeFCVTMU_32H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTMU  <Xd>, <Hn>
bool TryDecodeFCVTMU_64H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTMU  <Wd>, <Sn>
bool TryDecodeFCVTMU_32S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTMU  <Xd>, <Sn>
bool TryDecodeFCVTMU_64S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTMU  <Wd>, <Dn>
bool TryDecodeFCVTMU_32D_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTMU  <Xd>, <Dn>
bool TryDecodeFCVTMU_64D_FLOAT2INT(const InstData &data, Instruction &inst);

// LDP  <St1>, <St2>, [<Xn|SP>], #<imm>
bool TryDecodeLDP_S_LDSTPAIR_POST(const InstData &data, Instruction &inst);

// LDP  <Dt1>, <Dt2>, [<Xn|SP>], #<imm>
bool TryDecodeLDP_D_LDSTPAIR_POST(const InstData &data, Instruction &inst);

// LDP  <Qt1>, <Qt2>, [<Xn|SP>], #<imm>
bool TryDecodeLDP_Q_LDSTPAIR_POST(const InstData &data, Instruction &inst);

// LDP  <St1>, <St2>, [<Xn|SP>, #<imm>]!
bool TryDecodeLDP_S_LDSTPAIR_PRE(const InstData &data, Instruction &inst);

// LDP  <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!
bool TryDecodeLDP_D_LDSTPAIR_PRE(const InstData &data, Instruction &inst);

// LDP  <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!
bool TryDecodeLDP_Q_LDSTPAIR_PRE(const InstData &data, Instruction &inst);

// LDP  <St1>, <St2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeLDP_S_LDSTPAIR_OFF(const InstData &data, Instruction &inst);

// LDP  <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeLDP_D_LDSTPAIR_OFF(const InstData &data, Instruction &inst);

// LDP  <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeLDP_Q_LDSTPAIR_OFF(const InstData &data, Instruction &inst);

// SBC  <Wd>, <Wn>, <Wm>
bool TryDecodeSBC_32_ADDSUB_CARRY(const InstData &data, Instruction &inst);

// SBC  <Xd>, <Xn>, <Xm>
bool TryDecodeSBC_64_ADDSUB_CARRY(const InstData &data, Instruction &inst);

// FCVTZU  <Wd>, <Hn>
bool TryDecodeFCVTZU_32H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTZU  <Xd>, <Hn>
bool TryDecodeFCVTZU_64H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTZU  <Wd>, <Sn>
bool TryDecodeFCVTZU_32S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTZU  <Xd>, <Sn>
bool TryDecodeFCVTZU_64S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTZU  <Wd>, <Dn>
bool TryDecodeFCVTZU_32D_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTZU  <Xd>, <Dn>
bool TryDecodeFCVTZU_64D_FLOAT2INT(const InstData &data, Instruction &inst);

// CINV  <Wd>, <Wn>, <cond>
bool TryDecodeCINV_CSINV_32_CONDSEL(const InstData &data, Instruction &inst);

// CINV  <Xd>, <Xn>, <cond>
bool TryDecodeCINV_CSINV_64_CONDSEL(const InstData &data, Instruction &inst);

// STR  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeSTR_32_LDST_REGOFF(const InstData &data, Instruction &inst);

// STR  <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeSTR_64_LDST_REGOFF(const InstData &data, Instruction &inst);

// FDIV  <Hd>, <Hn>, <Hm>
bool TryDecodeFDIV_H_FLOATDP2(const InstData &data, Instruction &inst);

// FDIV  <Sd>, <Sn>, <Sm>
bool TryDecodeFDIV_S_FLOATDP2(const InstData &data, Instruction &inst);

// FDIV  <Dd>, <Dn>, <Dm>
bool TryDecodeFDIV_D_FLOATDP2(const InstData &data, Instruction &inst);

// URECPE  <Vd>.<T>, <Vn>.<T>
bool TryDecodeURECPE_ASIMDMISC_R(const InstData &data, Instruction &inst);

// ISB  {<option>|#<imm>}
bool TryDecodeISB_BI_SYSTEM(const InstData &data, Instruction &inst);

// RSUBHN{2}  <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>
bool TryDecodeRSUBHN_ASIMDDIFF_N(const InstData &data, Instruction &inst);

// SMULL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]
bool TryDecodeSMULL_ASIMDELEM_L(const InstData &data, Instruction &inst);

// SUQADD  <V><d>, <V><n>
bool TryDecodeSUQADD_ASISDMISC_R(const InstData &data, Instruction &inst);

// SUQADD  <Vd>.<T>, <Vn>.<T>
bool TryDecodeSUQADD_ASIMDMISC_R(const InstData &data, Instruction &inst);

// LDRSH  <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeLDRSH_32_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDRSH  <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeLDRSH_64_LDST_REGOFF(const InstData &data, Instruction &inst);

// ADRP  <Xd>, <label>
bool TryDecodeADRP_ONLY_PCRELADDR(const InstData &data, Instruction &inst);

// DUP  <Vd>.<T>, <R><n>
bool TryDecodeDUP_ASIMDINS_DR_R(const InstData &data, Instruction &inst);

// FABS  <Hd>, <Hn>
bool TryDecodeFABS_H_FLOATDP1(const InstData &data, Instruction &inst);

// FABS  <Sd>, <Sn>
bool TryDecodeFABS_S_FLOATDP1(const InstData &data, Instruction &inst);

// FABS  <Dd>, <Dn>
bool TryDecodeFABS_D_FLOATDP1(const InstData &data, Instruction &inst);

// REV32  <Vd>.<T>, <Vn>.<T>
bool TryDecodeREV32_ASIMDMISC_R(const InstData &data, Instruction &inst);

// AT  <at_op>, <Xt>
bool TryDecodeAT_SYS_CR_SYSTEM(const InstData &data, Instruction &inst);

// UQRSHRN  <Vb><d>, <Va><n>, #<shift>
bool TryDecodeUQRSHRN_ASISDSHF_N(const InstData &data, Instruction &inst);

// UQRSHRN{2}  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
bool TryDecodeUQRSHRN_ASIMDSHF_N(const InstData &data, Instruction &inst);

// UBFM  <Wd>, <Wn>, #<immr>, #<imms>
bool TryDecodeUBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// UBFM  <Xd>, <Xn>, #<immr>, #<imms>
bool TryDecodeUBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// STNP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeSTNP_32_LDSTNAPAIR_OFFS(const InstData &data, Instruction &inst);

// STNP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeSTNP_64_LDSTNAPAIR_OFFS(const InstData &data, Instruction &inst);

// LDARB  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDARB_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// SRSRA  <V><d>, <V><n>, #<shift>
bool TryDecodeSRSRA_ASISDSHF_R(const InstData &data, Instruction &inst);

// SRSRA  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeSRSRA_ASIMDSHF_R(const InstData &data, Instruction &inst);

// CMGE  <V><d>, <V><n>, <V><m>
bool TryDecodeCMGE_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// CMGE  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeCMGE_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFADD_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FADD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFADD_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// SQRDMLAH  <V><d>, <V><n>, <V><m>
bool TryDecodeSQRDMLAH_ASISDSAME2_ONLY(const InstData &data, Instruction &inst);

// SQRDMLAH  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSQRDMLAH_ASIMDSAME2_ONLY(const InstData &data, Instruction &inst);

// ORN  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeORN_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// STSETB  <Ws>, [<Xn|SP>]
bool TryDecodeSTSETB_32S_MEMOP(const InstData &data, Instruction &inst);

// STSETLB  <Ws>, [<Xn|SP>]
bool TryDecodeSTSETLB_32S_MEMOP(const InstData &data, Instruction &inst);

// ADC  <Wd>, <Wn>, <Wm>
bool TryDecodeADC_32_ADDSUB_CARRY(const InstData &data, Instruction &inst);

// ADC  <Xd>, <Xn>, <Xm>
bool TryDecodeADC_64_ADDSUB_CARRY(const InstData &data, Instruction &inst);

// BFC  <Wd>, #<lsb>, #<width>
bool TryDecodeBFC_BFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// BFC  <Xd>, #<lsb>, #<width>
bool TryDecodeBFC_BFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// LD2R  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]
bool TryDecodeLD2R_ASISDLSO_R2(const InstData &data, Instruction &inst);

// LD2R  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeLD2R_ASISDLSOP_R2_I(const InstData &data, Instruction &inst);

// LD2R  { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeLD2R_ASISDLSOP_RX2_R(const InstData &data, Instruction &inst);

// CSINC  <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSINC_32_CONDSEL(const InstData &data, Instruction &inst);

// CSINC  <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSINC_64_CONDSEL(const InstData &data, Instruction &inst);

// FMLS  <Hd>, <Hn>, <Vm>.H[<index>]
bool TryDecodeFMLS_ASISDELEM_RH_H(const InstData &data, Instruction &inst);

// FMLS  <V><d>, <V><n>, <Vm>.<Ts>[<index>]
bool TryDecodeFMLS_ASISDELEM_R_SD(const InstData &data, Instruction &inst);

// FMLS  <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>]
bool TryDecodeFMLS_ASIMDELEM_RH_H(const InstData &data, Instruction &inst);

// FMLS  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
bool TryDecodeFMLS_ASIMDELEM_R_SD(const InstData &data, Instruction &inst);

// SHA256H2  <Qd>, <Qn>, <Vm>.4S
bool TryDecodeSHA256H2_QQV_CRYPTOSHA3(const InstData &data, Instruction &inst);

// RBIT  <Vd>.<T>, <Vn>.<T>
bool TryDecodeRBIT_ASIMDMISC_R(const InstData &data, Instruction &inst);

// RSHRN{2}  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
bool TryDecodeRSHRN_ASIMDSHF_N(const InstData &data, Instruction &inst);

// UMOV  <Wd>, <Vn>.<Ts>[<index>]
bool TryDecodeUMOV_ASIMDINS_W_W(const InstData &data, Instruction &inst);

// UMOV  <Xd>, <Vn>.<Ts>[<index>]
bool TryDecodeUMOV_ASIMDINS_X_X(const InstData &data, Instruction &inst);

// FCVTZS  <Wd>, <Hn>
bool TryDecodeFCVTZS_32H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTZS  <Xd>, <Hn>
bool TryDecodeFCVTZS_64H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTZS  <Wd>, <Sn>
bool TryDecodeFCVTZS_32S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTZS  <Xd>, <Sn>
bool TryDecodeFCVTZS_64S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTZS  <Wd>, <Dn>
bool TryDecodeFCVTZS_32D_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTZS  <Xd>, <Dn>
bool TryDecodeFCVTZS_64D_FLOAT2INT(const InstData &data, Instruction &inst);

// NOP
bool TryDecodeNOP_HI_SYSTEM(const InstData &data, Instruction &inst);

// FCVTMS  <Hd>, <Hn>
bool TryDecodeFCVTMS_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTMS  <V><d>, <V><n>
bool TryDecodeFCVTMS_ASISDMISC_R(const InstData &data, Instruction &inst);

// FCVTMS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTMS_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTMS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTMS_ASIMDMISC_R(const InstData &data, Instruction &inst);

// FRINTA  <Hd>, <Hn>
bool TryDecodeFRINTA_H_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTA  <Sd>, <Sn>
bool TryDecodeFRINTA_S_FLOATDP1(const InstData &data, Instruction &inst);

// FRINTA  <Dd>, <Dn>
bool TryDecodeFRINTA_D_FLOATDP1(const InstData &data, Instruction &inst);

// FCSEL  <Hd>, <Hn>, <Hm>, <cond>
bool TryDecodeFCSEL_H_FLOATSEL(const InstData &data, Instruction &inst);

// FCSEL  <Sd>, <Sn>, <Sm>, <cond>
bool TryDecodeFCSEL_S_FLOATSEL(const InstData &data, Instruction &inst);

// FCSEL  <Dd>, <Dn>, <Dm>, <cond>
bool TryDecodeFCSEL_D_FLOATSEL(const InstData &data, Instruction &inst);

// SUBHN{2}  <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>
bool TryDecodeSUBHN_ASIMDDIFF_N(const InstData &data, Instruction &inst);

// LDRSB  <Wt>, [<Xn|SP>], #<simm>
bool TryDecodeLDRSB_32_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDRSB  <Xt>, [<Xn|SP>], #<simm>
bool TryDecodeLDRSB_64_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDRSB  <Wt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDRSB_32_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDRSB  <Xt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDRSB_64_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDRSB  <Wt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDRSB_32_LDST_POS(const InstData &data, Instruction &inst);

// LDRSB  <Xt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDRSB_64_LDST_POS(const InstData &data, Instruction &inst);

// FACGT  <Hd>, <Hn>, <Hm>
bool TryDecodeFACGT_ASISDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FACGT  <V><d>, <V><n>, <V><m>
bool TryDecodeFACGT_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// FACGT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFACGT_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FACGT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFACGT_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// NEG  <V><d>, <V><n>
bool TryDecodeNEG_ASISDMISC_R(const InstData &data, Instruction &inst);

// NEG  <Vd>.<T>, <Vn>.<T>
bool TryDecodeNEG_ASIMDMISC_R(const InstData &data, Instruction &inst);

// UMLAL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeUMLAL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// REV16  <Vd>.<T>, <Vn>.<T>
bool TryDecodeREV16_ASIMDMISC_R(const InstData &data, Instruction &inst);

// PMULL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodePMULL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// FMLS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMLS_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FMLS  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMLS_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// EOR  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeEOR_32_LOG_SHIFT(const InstData &data, Instruction &inst);

// EOR  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeEOR_64_LOG_SHIFT(const InstData &data, Instruction &inst);

// LDSMAXA  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAXA_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMAXAL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAXAL_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMAX  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAX_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMAXL  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAXL_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMAXA  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSMAXA_64_MEMOP(const InstData &data, Instruction &inst);

// LDSMAXAL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSMAXAL_64_MEMOP(const InstData &data, Instruction &inst);

// LDSMAX  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSMAX_64_MEMOP(const InstData &data, Instruction &inst);

// LDSMAXL  <Xs>, <Xt>, [<Xn|SP>]
bool TryDecodeLDSMAXL_64_MEMOP(const InstData &data, Instruction &inst);

// SYS  #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}
bool TryDecodeSYS_CR_SYSTEM(const InstData &data, Instruction &inst);

// SQABS  <V><d>, <V><n>
bool TryDecodeSQABS_ASISDMISC_R(const InstData &data, Instruction &inst);

// SQABS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeSQABS_ASIMDMISC_R(const InstData &data, Instruction &inst);

// LDAR  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeLDAR_LR32_LDSTEXCL(const InstData &data, Instruction &inst);

// LDAR  <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeLDAR_LR64_LDSTEXCL(const InstData &data, Instruction &inst);

// STADDH  <Ws>, [<Xn|SP>]
bool TryDecodeSTADDH_32S_MEMOP(const InstData &data, Instruction &inst);

// STADDLH  <Ws>, [<Xn|SP>]
bool TryDecodeSTADDLH_32S_MEMOP(const InstData &data, Instruction &inst);

// LDRSW  <Xt>, [<Xn|SP>], #<simm>
bool TryDecodeLDRSW_64_LDST_IMMPOST(const InstData &data, Instruction &inst);

// LDRSW  <Xt>, [<Xn|SP>, #<simm>]!
bool TryDecodeLDRSW_64_LDST_IMMPRE(const InstData &data, Instruction &inst);

// LDRSW  <Xt>, [<Xn|SP>{, #<pimm>}]
bool TryDecodeLDRSW_64_LDST_POS(const InstData &data, Instruction &inst);

// FCVTAS  <Hd>, <Hn>
bool TryDecodeFCVTAS_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTAS  <V><d>, <V><n>
bool TryDecodeFCVTAS_ASISDMISC_R(const InstData &data, Instruction &inst);

// FCVTAS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTAS_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTAS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTAS_ASIMDMISC_R(const InstData &data, Instruction &inst);

// UQSHRN  <Vb><d>, <Va><n>, #<shift>
bool TryDecodeUQSHRN_ASISDSHF_N(const InstData &data, Instruction &inst);

// UQSHRN{2}  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
bool TryDecodeUQSHRN_ASIMDSHF_N(const InstData &data, Instruction &inst);

// EXT  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>
bool TryDecodeEXT_ASIMDEXT_ONLY(const InstData &data, Instruction &inst);

// USHL  <V><d>, <V><n>, <V><m>
bool TryDecodeUSHL_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// USHL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeUSHL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FADDP  <V><d>, <Vn>.<T>
bool TryDecodeFADDP_ASISDPAIR_ONLY_H(const InstData &data, Instruction &inst);

// FADDP  <V><d>, <Vn>.<T>
bool TryDecodeFADDP_ASISDPAIR_ONLY_SD(const InstData &data, Instruction &inst);

// SSHR  <V><d>, <V><n>, #<shift>
bool TryDecodeSSHR_ASISDSHF_R(const InstData &data, Instruction &inst);

// SSHR  <Vd>.<T>, <Vn>.<T>, #<shift>
bool TryDecodeSSHR_ASIMDSHF_R(const InstData &data, Instruction &inst);

// SHSUB  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeSHSUB_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// CMN  <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
bool TryDecodeCMN_ADDS_32S_ADDSUB_EXT(const InstData &data, Instruction &inst);

// CMN  <Xn|SP>, <R><m>{, <extend> {#<amount>}}
bool TryDecodeCMN_ADDS_64S_ADDSUB_EXT(const InstData &data, Instruction &inst);

// FMINNM  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMINNM_ASIMDSAMEFP16_ONLY(const InstData &data,
                                        Instruction &inst);

// FMINNM  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFMINNM_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// UMLSL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeUMLSL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// USHLL{2}  <Vd>.<Ta>, <Vn>.<Tb>, #<shift>
bool TryDecodeUSHLL_ASIMDSHF_L(const InstData &data, Instruction &inst);

// STLR  <Wt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLR_SL32_LDSTEXCL(const InstData &data, Instruction &inst);

// STLR  <Xt>, [<Xn|SP>{,#0}]
bool TryDecodeSTLR_SL64_LDSTEXCL(const InstData &data, Instruction &inst);

// EON  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeEON_32_LOG_SHIFT(const InstData &data, Instruction &inst);

// EON  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeEON_64_LOG_SHIFT(const InstData &data, Instruction &inst);

// STSMAXB  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMAXB_32S_MEMOP(const InstData &data, Instruction &inst);

// STSMAXLB  <Ws>, [<Xn|SP>]
bool TryDecodeSTSMAXLB_32S_MEMOP(const InstData &data, Instruction &inst);

// FCVTNS  <Wd>, <Hn>
bool TryDecodeFCVTNS_32H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTNS  <Xd>, <Hn>
bool TryDecodeFCVTNS_64H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTNS  <Wd>, <Sn>
bool TryDecodeFCVTNS_32S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTNS  <Xd>, <Sn>
bool TryDecodeFCVTNS_64S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTNS  <Wd>, <Dn>
bool TryDecodeFCVTNS_32D_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTNS  <Xd>, <Dn>
bool TryDecodeFCVTNS_64D_FLOAT2INT(const InstData &data, Instruction &inst);

// SQSHRN  <Vb><d>, <Va><n>, #<shift>
bool TryDecodeSQSHRN_ASISDSHF_N(const InstData &data, Instruction &inst);

// SQSHRN{2}  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
bool TryDecodeSQSHRN_ASIMDSHF_N(const InstData &data, Instruction &inst);

// LDTRB  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDTRB_32_LDST_UNPRIV(const InstData &data, Instruction &inst);

// LDRSB  <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
bool TryDecodeLDRSB_32B_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDRSB  <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
bool TryDecodeLDRSB_32BL_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDRSB  <Xt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
bool TryDecodeLDRSB_64B_LDST_REGOFF(const InstData &data, Instruction &inst);

// LDRSB  <Xt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
bool TryDecodeLDRSB_64BL_LDST_REGOFF(const InstData &data, Instruction &inst);

// SXTH  <Wd>, <Wn>
bool TryDecodeSXTH_SBFM_32M_BITFIELD(const InstData &data, Instruction &inst);

// SXTH  <Xd>, <Wn>
bool TryDecodeSXTH_SBFM_64M_BITFIELD(const InstData &data, Instruction &inst);

// LDURSB  <Wt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDURSB_32_LDST_UNSCALED(const InstData &data, Instruction &inst);

// LDURSB  <Xt>, [<Xn|SP>{, #<simm>}]
bool TryDecodeLDURSB_64_LDST_UNSCALED(const InstData &data, Instruction &inst);

// SHA256H  <Qd>, <Qn>, <Vm>.4S
bool TryDecodeSHA256H_QQV_CRYPTOSHA3(const InstData &data, Instruction &inst);

// LD4R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]
bool TryDecodeLD4R_ASISDLSO_R4(const InstData &data, Instruction &inst);

// LD4R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeLD4R_ASISDLSOP_R4_I(const InstData &data, Instruction &inst);

// LD4R  { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeLD4R_ASISDLSOP_RX4_R(const InstData &data, Instruction &inst);

// FCVTNS  <Hd>, <Hn>
bool TryDecodeFCVTNS_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTNS  <V><d>, <V><n>
bool TryDecodeFCVTNS_ASISDMISC_R(const InstData &data, Instruction &inst);

// FCVTNS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTNS_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FCVTNS  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFCVTNS_ASIMDMISC_R(const InstData &data, Instruction &inst);

// FDIV  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFDIV_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FDIV  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFDIV_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// FRECPE  <Hd>, <Hn>
bool TryDecodeFRECPE_ASISDMISCFP16_R(const InstData &data, Instruction &inst);

// FRECPE  <V><d>, <V><n>
bool TryDecodeFRECPE_ASISDMISC_R(const InstData &data, Instruction &inst);

// FRECPE  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRECPE_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FRECPE  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRECPE_ASIMDMISC_R(const InstData &data, Instruction &inst);

// LD1R  { <Vt>.<T> }, [<Xn|SP>]
bool TryDecodeLD1R_ASISDLSO_R1(const InstData &data, Instruction &inst);

// LD1R  { <Vt>.<T> }, [<Xn|SP>], <imm>
bool TryDecodeLD1R_ASISDLSOP_R1_I(const InstData &data, Instruction &inst);

// LD1R  { <Vt>.<T> }, [<Xn|SP>], <Xm>
bool TryDecodeLD1R_ASISDLSOP_RX1_R(const InstData &data, Instruction &inst);

// MUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
bool TryDecodeMUL_ASIMDELEM_R(const InstData &data, Instruction &inst);

// UADDLV  <V><d>, <Vn>.<T>
bool TryDecodeUADDLV_ASIMDALL_ONLY(const InstData &data, Instruction &inst);

// FNEG  <Hd>, <Hn>
bool TryDecodeFNEG_H_FLOATDP1(const InstData &data, Instruction &inst);

// FNEG  <Sd>, <Sn>
bool TryDecodeFNEG_S_FLOATDP1(const InstData &data, Instruction &inst);

// FNEG  <Dd>, <Dn>
bool TryDecodeFNEG_D_FLOATDP1(const InstData &data, Instruction &inst);

// USUBL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeUSUBL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// SHA1C  <Qd>, <Sn>, <Vm>.4S
bool TryDecodeSHA1C_QSV_CRYPTOSHA3(const InstData &data, Instruction &inst);

// SQDMLSL  <Va><d>, <Vb><n>, <Vb><m>
bool TryDecodeSQDMLSL_ASISDDIFF_ONLY(const InstData &data, Instruction &inst);

// SQDMLSL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeSQDMLSL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// PRFUM (<prfop>|#<imm5>), [<Xn|SP>{, #<simm>}]
bool TryDecodePRFUM_P_LDST_UNSCALED(const InstData &data, Instruction &inst);

// LDSMAXAB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAXAB_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMAXALB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAXALB_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMAXB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAXB_32_MEMOP(const InstData &data, Instruction &inst);

// LDSMAXLB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDSMAXLB_32_MEMOP(const InstData &data, Instruction &inst);

// FABD  <Hd>, <Hn>, <Hm>
bool TryDecodeFABD_ASISDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FABD  <V><d>, <V><n>, <V><m>
bool TryDecodeFABD_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// FABD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFABD_ASIMDSAMEFP16_ONLY(const InstData &data, Instruction &inst);

// FABD  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeFABD_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// B.<cond>  <label>
bool TryDecodeB_ONLY_CONDBRANCH(const InstData &data, Instruction &inst);

// FCVTNU  <Wd>, <Hn>
bool TryDecodeFCVTNU_32H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTNU  <Xd>, <Hn>
bool TryDecodeFCVTNU_64H_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTNU  <Wd>, <Sn>
bool TryDecodeFCVTNU_32S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTNU  <Xd>, <Sn>
bool TryDecodeFCVTNU_64S_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTNU  <Wd>, <Dn>
bool TryDecodeFCVTNU_32D_FLOAT2INT(const InstData &data, Instruction &inst);

// FCVTNU  <Xd>, <Dn>
bool TryDecodeFCVTNU_64D_FLOAT2INT(const InstData &data, Instruction &inst);

// MUL  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeMUL_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// UDIV  <Wd>, <Wn>, <Wm>
bool TryDecodeUDIV_32_DP_2SRC(const InstData &data, Instruction &inst);

// UDIV  <Xd>, <Xn>, <Xm>
bool TryDecodeUDIV_64_DP_2SRC(const InstData &data, Instruction &inst);

// CMTST  <V><d>, <V><n>, <V><m>
bool TryDecodeCMTST_ASISDSAME_ONLY(const InstData &data, Instruction &inst);

// CMTST  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeCMTST_ASIMDSAME_ONLY(const InstData &data, Instruction &inst);

// UADDL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeUADDL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// MOV  <Wd>, #<imm>
bool TryDecodeMOV_MOVN_32_MOVEWIDE(const InstData &data, Instruction &inst);

// MOV  <Xd>, #<imm>
bool TryDecodeMOV_MOVN_64_MOVEWIDE(const InstData &data, Instruction &inst);

// TRN2  <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
bool TryDecodeTRN2_ASIMDPERM_ONLY(const InstData &data, Instruction &inst);

// MOVK  <Wd>, #<imm>{, LSL #<shift>}
bool TryDecodeMOVK_32_MOVEWIDE(const InstData &data, Instruction &inst);

// MOVK  <Xd>, #<imm>{, LSL #<shift>}
bool TryDecodeMOVK_64_MOVEWIDE(const InstData &data, Instruction &inst);

// SMADDL  <Xd>, <Wn>, <Wm>, <Xa>
bool TryDecodeSMADDL_64WA_DP_3SRC(const InstData &data, Instruction &inst);

// AND  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeAND_32_LOG_SHIFT(const InstData &data, Instruction &inst);

// AND  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeAND_64_LOG_SHIFT(const InstData &data, Instruction &inst);

// SQSHRUN  <Vb><d>, <Va><n>, #<shift>
bool TryDecodeSQSHRUN_ASISDSHF_N(const InstData &data, Instruction &inst);

// SQSHRUN{2}  <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
bool TryDecodeSQSHRUN_ASIMDSHF_N(const InstData &data, Instruction &inst);

// SQDMULL  <Va><d>, <Vb><n>, <Vb><m>
bool TryDecodeSQDMULL_ASISDDIFF_ONLY(const InstData &data, Instruction &inst);

// SQDMULL{2}  <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>
bool TryDecodeSQDMULL_ASIMDDIFF_L(const InstData &data, Instruction &inst);

// FNMADD  <Hd>, <Hn>, <Hm>, <Ha>
bool TryDecodeFNMADD_H_FLOATDP3(const InstData &data, Instruction &inst);

// FNMADD  <Sd>, <Sn>, <Sm>, <Sa>
bool TryDecodeFNMADD_S_FLOATDP3(const InstData &data, Instruction &inst);

// FNMADD  <Dd>, <Dn>, <Dm>, <Da>
bool TryDecodeFNMADD_D_FLOATDP3(const InstData &data, Instruction &inst);

// FCCMP  <Hn>, <Hm>, #<nzcv>, <cond>
bool TryDecodeFCCMP_H_FLOATCCMP(const InstData &data, Instruction &inst);

// FCCMP  <Sn>, <Sm>, #<nzcv>, <cond>
bool TryDecodeFCCMP_S_FLOATCCMP(const InstData &data, Instruction &inst);

// FCCMP  <Dn>, <Dm>, #<nzcv>, <cond>
bool TryDecodeFCCMP_D_FLOATCCMP(const InstData &data, Instruction &inst);

// LD3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>]
bool TryDecodeLD3_ASISDLSO_B3_3B(const InstData &data, Instruction &inst);

// LD3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>]
bool TryDecodeLD3_ASISDLSO_H3_3H(const InstData &data, Instruction &inst);

// LD3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>]
bool TryDecodeLD3_ASISDLSO_S3_3S(const InstData &data, Instruction &inst);

// LD3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>]
bool TryDecodeLD3_ASISDLSO_D3_3D(const InstData &data, Instruction &inst);

// LD3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3
bool TryDecodeLD3_ASISDLSOP_B3_I3B(const InstData &data, Instruction &inst);

// LD3  { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD3_ASISDLSOP_BX3_R3B(const InstData &data, Instruction &inst);

// LD3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6
bool TryDecodeLD3_ASISDLSOP_H3_I3H(const InstData &data, Instruction &inst);

// LD3  { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD3_ASISDLSOP_HX3_R3H(const InstData &data, Instruction &inst);

// LD3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12
bool TryDecodeLD3_ASISDLSOP_S3_I3S(const InstData &data, Instruction &inst);

// LD3  { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD3_ASISDLSOP_SX3_R3S(const InstData &data, Instruction &inst);

// LD3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24
bool TryDecodeLD3_ASISDLSOP_D3_I3D(const InstData &data, Instruction &inst);

// LD3  { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm>
bool TryDecodeLD3_ASISDLSOP_DX3_R3D(const InstData &data, Instruction &inst);

// FRINTN  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTN_ASIMDMISCFP16_R(const InstData &data, Instruction &inst);

// FRINTN  <Vd>.<T>, <Vn>.<T>
bool TryDecodeFRINTN_ASIMDMISC_R(const InstData &data, Instruction &inst);

// SUB  <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
bool TryDecodeSUB_32_ADDSUB_EXT(const InstData &data, Instruction &inst);

// SUB  <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}
bool TryDecodeSUB_64_ADDSUB_EXT(const InstData &data, Instruction &inst);

// STR  <Bt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]
bool TryDecodeSTR_B_LDST_REGOFF(const InstData &data, Instruction &inst);

// STR  <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}]
bool TryDecodeSTR_BL_LDST_REGOFF(const InstData &data, Instruction &inst);

// STR  <Ht>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeSTR_H_LDST_REGOFF(const InstData &data, Instruction &inst);

// STR  <St>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeSTR_S_LDST_REGOFF(const InstData &data, Instruction &inst);

// STR  <Dt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeSTR_D_LDST_REGOFF(const InstData &data, Instruction &inst);

// STR  <Qt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
bool TryDecodeSTR_Q_LDST_REGOFF(const InstData &data, Instruction &inst);

// STP  <Wt1>, <Wt2>, [<Xn|SP>], #<imm>
bool TryDecodeSTP_32_LDSTPAIR_POST(const InstData &data, Instruction &inst);

// STP  <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
bool TryDecodeSTP_64_LDSTPAIR_POST(const InstData &data, Instruction &inst);

// STP  <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!
bool TryDecodeSTP_32_LDSTPAIR_PRE(const InstData &data, Instruction &inst);

// STP  <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
bool TryDecodeSTP_64_LDSTPAIR_PRE(const InstData &data, Instruction &inst);

// STP  <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeSTP_32_LDSTPAIR_OFF(const InstData &data, Instruction &inst);

// STP  <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
bool TryDecodeSTP_64_LDSTPAIR_OFF(const InstData &data, Instruction &inst);

// ORN  <Wd>, <Wn>, <Wm>{, <shift> #<amount>}
bool TryDecodeORN_32_LOG_SHIFT(const InstData &data, Instruction &inst);

// ORN  <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
bool TryDecodeORN_64_LOG_SHIFT(const InstData &data, Instruction &inst);

// LDCLRAB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLRAB_32_MEMOP(const InstData &data, Instruction &inst);

// LDCLRALB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLRALB_32_MEMOP(const InstData &data, Instruction &inst);

// LDCLRB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLRB_32_MEMOP(const InstData &data, Instruction &inst);

// LDCLRLB  <Ws>, <Wt>, [<Xn|SP>]
bool TryDecodeLDCLRLB_32_MEMOP(const InstData &data, Instruction &inst);


const char *InstNameToString(InstName iclass);
const char *InstFormToString(InstForm iform);

bool TryExtract(const uint8_t *bytes, InstData &data);
bool TryDecode(const InstData &data, Instruction &inst);

}  // namespace aarch64
}  // namespace remill
